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| DATA SHEET PD754144, 754244 4-BIT SINGLE-CHIP MICROCONTROLLERS MOS INTEGRATED CIRCUIT DESCRIPTION The PD754244 is a 4-bit single-chip microcontroller which incorporates the EEPROMTM for key-less entry application. It incorporates a 16 x 8-bit EEPROM, a 4-Kbyte mask ROM to store software, a 128 x 4-bit RAM to store the processing data, a processing CPU, and a carrier generator which easily outputs waveforms for infrared remote controller. The details of functions are described in the following user's manual. Be sure to read it before designing. PD754144, 754244 User's Manual: U10676E FEATURES * * * * * * * On-chip EEPROM: 16 x 8 bits (mapped to the data memory) On-chip key return reset function for key-less entry System clock oscillation circuit * PD754144: RC oscillator (external resistor and capacitor) * PD754244: Crystal/ceramic oscillator Low-voltage operation: VDD = 1.8 to 6.0 V Timer function (4 channels) * Basic interval timer/watchdog timer: 1 channel * 8-bit timer counter : 3 channels On-chip memory * Program memory (ROM) 4096 x 8 bits * Data memory (static RAM) 128 x 4 bits Instruction execution time variable function suited for power saving. * PD754144: 4, 8, 16, 64 s (at fcc = 1.0-MHz operation) * PD754244: 0.95, 1.91, 3.81, 15.3 s (at fx = 4.19-MHz operation) 0.67, 1.33, 2.67, 10.7 s (at fx = 6.0-MHz operation) APPLICATIONS Automotive appliances such as key-less entry, compact data carrier, etc. Unless contextually excluded, references in this data sheet to the PD754244 (crystal/ceramic oscillation: fX) mean the PD754144. The PD754144 and PD754244 differ in the notation of their RC oscillation: whenever fX (RC oscillation notation for PD754244) is described, fCC should be substituted for the PD754144. The information in this document is subject to change without notice. Document No. U10040EJ2V0DS00 Date Published July 1998 N CP(K) Printed in Japan The mark shows major revised points. (c) 1995 PD754144, 754244 ORDERING INFORMATION Part Number Package 20-pin plastic SOP (300 mil, 1.27-mm pitch) 20-pin plastic shrink SOP (300 mil, 0.65-mm pitch) 20-pin plastic SOP (300 mil, 1.27-mm pitch) 20-pin plastic shrink SOP (300 mil, 0.65-mm pitch) PD754144GS-xxx-BA5 PD754144GS-xxx-GJG PD754244GS-xxx-BA5 PD754244GS-xxx-GJG Remark xxx indicates ROM code suffix. 2 PD754144, 754244 Functional Outline Parameter Instruction execution time PD754144 * 4, 8, 16, 64 s (at fcc = 1.0-MHz operation) PD754244 * 0.95, 1.91, 3.81, 15.3 s (at fx = 4.19-MHz operation) * 0.67, 1.33, 2.67, 10.7 s (at fx = 6.0-MHz operation) On-chip memory Mask ROM RAM EEPROM 4096 x 8 bits (0000H-0FFFH) 128 x 4 bits (000H-07FH) 16 x 8 bits (400H-41FH) RC oscillator (External resistor and capacitor) * 4-bit operation: 8 x 4 banks * 8-bit operation: 4 x 4 banks 4 9 13 56/fcc 2 /fcc 9 System clock oscillator Crystal/ceramic oscillator General-purpose register Input/output port CMOS input CMOS input/output Total On-chip pull-up resistor can be specified by mask option. On-chip pull-up resistor connection can be specified by means of software. Start-up time after reset Stand-by mode release time 217/fx, 215/fx (selected by mask option) 2 /fx, 2 /fx, 2 /fx, 2 /fx (selected by the setting of BTM) 20 17 15 13 Timer 4 channels * 8-bit timer counter (can be used as 16-bit timer counter) * Basic interval/watchdog timer : 3 channels : 1 channel Bit sequential buffer Vectored interrupt Test input Standby function Operating ambient temperature Operating supply voltage Package 16 bits External: 1, Internal: 5 External: 1 (key return reset function available) STOP/HALT mode TA = -40 to +85 C VDD = 1.8 to 6.0 V * 20-pin plastic SOP (300 mil, 1.27-mm pitch) * 20-pin plastic shrink SOP (300 mil, 0.65-mm pitch) 3 PD754144, 754244 CONTENTS 1. PIN CONFIGURATION (TOP VIEW) .................................................................................................... 6 2. BLOCK DIAGRAM ................................................................................................................................ 8 3. PIN FUNCTION ..................................................................................................................................... 9 3.1 Port Pins ...................................................................................................................................... 9 3.2 Non-port Pins ............................................................................................................................ 10 3.3 Pin Input/Output Circuits ......................................................................................................... 11 3.4 Recommended Connection of Unused Pins .......................................................................... 12 4. SWITCHING FUNCTION BETWEEN MK I MODE AND MK II MODE ............................................... 13 4.1 Difference between Mk I and Mk II Modes .............................................................................. 13 4.2 Setting Method of Stack Bank Select Register (SBS) ........................................................... 14 5. MEMORY CONFIGURATION ............................................................................................................. 15 6. EEPROM .............................................................................................................................................18 7. PERIPHERAL HARDWARE FUNCTIONS ......................................................................................... 19 7.1 Digital Input/Output Ports ........................................................................................................ 19 7.2 Clock Generator ........................................................................................................................19 7.3 Basic Interval Timer/Watchdog Timer ..................................................................................... 22 7.4 Timer Counter ........................................................................................................................... 23 7.5 Programmable Threshold Port (Analog Input Port) ............................................................... 27 7.6 Bit Sequential Buffer ....... 16 Bits ............................................................................................ 28 8. INTERRUPT FUNCTION AND TEST FUNCTION .............................................................................. 29 9. STANDBY FUNCTION ........................................................................................................................31 10. RESET FUNCTION .............................................................................................................................32 10.1 Configuration and Operation Status of RESET Function ..................................................... 32 10.2 Watchdog Flag (WDF), Key Return Flag (KRF) ...................................................................... 36 11. MASK OPTION ...................................................................................................................................38 12. INSTRUCTION SETS ..........................................................................................................................39 13. ELECTRICAL SPECIFICATIONS ...................................................................................................... 48 13.1 PD754144 ................................................................................................................................. 48 13.2 PD754244 ................................................................................................................................. 56 14. CHARACTERISTICS CURVES (REFERENCE VALUES) ................................................................. 67 14.1 PD754144 ................................................................................................................................. 67 14.2 PD754244 ................................................................................................................................. 69 4 PD754144, 754244 15. RC OSCILLATION FREQUENCY CHARACTERISTICS EXAMPLES (REFERENCE VALUES) ..... 72 16. PACKAGE DRAWINGS ...................................................................................................................... 76 17. RECOMMENDED SOLDERING CONDITIONS .................................................................................. 78 APPENDIX A. COMPARISON OF FUNCTIONS AMONG PD754144, 754244, AND 75F4264 ........... 80 APPENDIX B. DEVELOPMENT TOOLS ................................................................................................. 81 APPENDIX C. RELATED DOCUMENTS ................................................................................................84 5 PD754144, 754244 1. PIN CONFIGURATION (TOP VIEW) * PD754144 * 20-pin Plastic SOP (300 mil, 1.27-mm pitch) PD754144GS-xxx-BA5 * 20-pin Plastic Shrink SOP (300 mil, 0.65-mm pitch) PD754144GS-xxx-GJG RESET CL1 CL2 VSS IC VDD P60/AVREF P61/INT0 P62/PTH00 P63/PTH01 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 KRREN P80 P30/PTO0 P31/PTO1 P32/PTO2 P33 P70/KR4 P71/KR5 P72/KR6 P73/KR7 IC: Internally Connected (Connect to VDD directly) 6 PD754144, 754244 * PD754244 * 20-pin Plastic SOP (300 mil, 1.27-mm pitch) PD754244GS-xxx-BA5 * 20-pin Plastic Shrink SOP (300 mil, 0.65-mm pitch) PD754244GS-xxx-GJG RESET X1 X2 VSS IC VDD P60/AVREF P61/INT0 P62/PTH00 P63/PTH01 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 KRREN P80 P30/PTO0 P31/PTO1 P32/PTO2 P33 P70/KR4 P71/KR5 P72/KR6 P73/KR7 IC: Internally Connected (Connect to VDD directly) Pin Identification AVREF CL1 and CL2 IC INT0 KR4 to KR7 KRREN P30 to P33 P60 to P63 : Analog reference : System clock (RC) : Internally connected : External vectored interrupt 0 : Key returns 4 to 7 : Key return reset enable : Port 3 : Port 6 P70 to P73 P80 PTH00 and PTH01 PTO0 to PTO2 RESET VDD VSS X1 and X2 : Port 7 : Port 8 : Programmable threshold port analog inputs 0 and 1 : Programmable timer outputs 0 to 2 : Reset : Positive power supply : Ground : System clock (crystal/ceramic) 7 PD754144, 754244 2. BLOCK DIAGRAM BASIC INTERVAL TIMER/WATCHDOG TIMER SP (8) INTBT RESET ALU PTO0/P30 8-BIT TIMER COUNTER#0 INTT0 TOUT PROGRAM COUNTER INTT1 8-BIT TIMER COUNTER#1 CASCADED PORT3 4 P30 to P33 CY PORT6 4 P60 to P63 SBS BANK PORT7 4 P70 to P73 PTO1/P31 GENERAL REG. PTO2/P32 8-BIT TIMER COUNTER#2 16-BIT TIMER COUNTER PROGRAM MEMORY (ROM) 4096x8 BITS DATA MEMORY (RAM) 128x4 BITS PORT8 P80 INTT2 EEPROM 16x8 BITS INT0/P61 DECODE AND CONTROL BIT SEQ. BUFFER (16) KRREN KR4/P70 to 4 KR7/P73 INTERRUPT CONTROL fX/2N AVREF/P60 PTH00/P62 PTH01/P63 PROGRAMMABLE THRESHOLD PORT CPU CLOCK CLOCK SYSTEM CLOCK STAND BY DIVIDER GENERATOR CONTROL CL1 CL2 X1 X2 Apply to the Apply to the PD754144 PD754244 IC VDD VSS RESET 8 PD754144, 754244 3. PIN FUNCTION 3.1 Port Pins Alternate Function PTO0 PTO1 PTO2 - Input/Output AVREF INT0 PTH00 PTH01 Input KR4 KR5 KR6 KR7 Input/Output - 1-bit input/output port (PORT8). On-chip pull-up resistor connection can be specified by software. - Input F -A 8-bit I/O - I/O Circuit TYPE Note 1 E-B Pin Name P30 P31 P32 P33 P60 P61 P62 P63 P70 P71 P72 P73 P80 Input/Output Input/Output Function Programmable 4-bit input/output port (PORT3). This port can be specified input/output bitwise. On-chip pull-up resistor connection can be specified by software in 4-bit units. Programmable 4-bit input/output port (PORT6). This port can be specified input/output bitwise. On-chip pull-up resistor can be specified by Note2 software in 4-bit units . Noise eliminator can be selected with P61/INT0. 4-bit input port (PORT7). On-chip pull-up resistor can be specified by software bit-wise. After Reset Input - Input F -A - Input B -A Notes 1. 2. Circled characters indicate the Schmitt-trigger input. Do not specify an on-chip pull-up resistor connection when using the programmable threshold port. 9 PD754144, 754244 3.2 Non-port Pins Alternate Function P30 P31 P32 Input P61 Edge detection vectored interrupt input pin (detected edge can be selected) Noise elimination circuit can be selected. Noise elimination circuit can be selected. Asynchronous input Input F -A I/O Circuit TYPENote E-B Pin Name PTO0 PTO1 PTO2 INT0 Input/Output Output Function Timer counter output pins After Reset Input KR4 to KR7 PTH00 PTH01 KRREN Input Input P70 to P73 P62 P63 Falling edge detection testable input pins Threshold voltage-variable 2-bit analog input pins Input Input B -A F -A Input - Key return reset enable pin The reset signal is generated at the falling edge of KRn while KRREN is high in STOP mode. Reference voltage input pin Incorporated in the PD754144 only RC (for system clock oscillation) connection pin External clock cannot be input. Input B AVREF CL1 CL2 X1 Input - - Input P60 - Input F -A - - - Incorporated in the PD754244 only Crystal/ceramic resonator (for system clock oscillation) connection pin When inputting the external clock, input the external clock to pin X1 and input the inverted phase of the external clock to pin X2. - - X2 - RESET Input - System reset input pin (low-level active) Pull-up resistor can be incorporated (mask option). - B -A IC VDD VSS - - - - - - Internally Connected Positive supply pin Ground potential Connect directly to VDD. - - - - - - Note Circled characters indicate the Schmitt-trigger input. 10 PD754144, 754244 3.3 Pin Input/Output Circuits The PD754244 pin input/output circuits are shown schematically. TYPE A TYPE D VDD VDD data P-ch IN N-ch output disable N-ch P-ch OUT CMOS specification input buffer. TYPE B Push-pull output that can be placed in output high-impedance (both P-ch, N-ch off). TYPE E-B VDD P.U.R. P.U.R. enable data Type D output disable P-ch IN IN/OUT Schmitt-trigger input having hysteresis characteristic. Type A P.U.R. : Pull-Up Resistor TYPE B-A TYPE F-A VDD VDD P.U.R. (Mask Option) P.U.R. enable data IN output disable Type D P.U.R. P-ch IN/OUT P.U.R. : Pull-Up Resistor Type B P.U.R. : Pull-Up Resistor 11 PD754144, 754244 3.4 Recommended Connection of Unused Pins Table 3-1. List of Recommended Connection of Unused Pins Pin P30/PTO0 P31/PTO1 P32/PTO2 P33 P60/AVREF P61/INT0 P62/PTH00 P63/PTH01 P70/KR4 P71/KR5 P72/KR6 P73/KR7 P80 Input state : Independently connect to VSS or VDD via a resistor. Output state: Leave open. KRREN When this pin is connected to VDD, internal reset signal is generated at the falling edge of the KRn pin in the STOP mode. When this pin is connected to VSS, internal reset signal is not generated even if the falling edge of KRn pin is detected in the STOP mode. Connect directly to VDD. Connect to VDD. Recommended Connecting Method Input state : Independently connect to VSS or VDD via a resistor. Output state: Leave open. IC 12 PD754144, 754244 4. SWITCHING FUNCTION BETWEEN MK I MODE AND MK II MODE 4.1 Difference between Mk I and Mk II Modes The PD754244 75XL CPU has the following two modes: Mk I and Mk II, either of which can be selected. The mode can be switched by the bit 3 of the Stack Bank Select register (SBS). * Mk I mode: * Mk II mode: Instructions are compatible with the 75X series. Can be used in the 75XL CPU with a ROM capacity of up to 16 Kbytes. Incompatible with 75X series. Can be used in all the 75XL CPU's including those products whose ROM capacity is more than 16 Kbytes. Table 4-1. Differences between Mk I Mode and Mk II Mode Mk I Mode Number of stack bytes for subroutine instructions BRA !addr1 instruction CALLA !addr1 instruction CALL !addr instruction CALLF !faddr instruction 2 bytes 3 bytes Mk II Mode Not available Available 3 machine cycles 2 machine cycles 4 machine cycles 3 machine cycles Caution The Mk II mode supports a program area exceeding 16 Kbytes for the 75X and 75XL Series. Therefore, this mode is effective for enhancing software compatibility with products that have a program area of more than 16 Kbytes. With regard to the number of stack bytes during execution of subroutine call instructions, the usable area increases by 1 byte per stack compared to the Mk I mode when the Mk II mode is selected. However, when the CALL !addr and CALLF !faddr instructions are used, the machine cycle becomes longer by 1 machine cycle. Therefore, if more emphasis is placed on RAM use efficiency and processing performance than on software compatibility, the Mk I mode should be used. 13 PD754144, 754244 4.2 Setting Method of Stack Bank Select Register (SBS) Switching between the Mk I mode and Mk II mode can be done by the SBS. Figure 4-1 shows the format. The SBS is set by a 4-bit memory manipulation instruction. When using the Mk I mode, the SBS must be initialized to 1000B at the beginning of a program. When using the Mk II mode, it must be initialized to 0000B. Figure 4-1. Stack Bank Select Register Format Address F84H 3 SBS3 2 1 0 SBS0 Symbol SBS SBS2 SBS1 Stack area specification 0 0 Memory bank 0 Other than above setting prohibited 0 0 must be set in the bit 2 position Mode switching specification 0 1 Mk II mode Mk I mode Caution Because SBS. 3 is set to "1" after a RESET signal is generated, the CPU operates in the Mk I mode. When executing an instruction in the Mk II mode, set SBS. 3 to "0" to select the Mk II mode. 14 PD754144, 754244 5. MEMORY CONFIGURATION * Program memory (ROM) * *** 4096 x 8 bits Addresses 0000H and 0001H Vector table wherein the program start address and the values set for the RBE and MBE at the time a RESET signal is generated are written. Reset and start are possible at an arbitrary address. * Addresses 0002H to 000FH Vector table wherein the program start address and values set for the RBE and MBE by the vectored interrupts are written. Interrupt service can be started at an arbitrary address. * Addresses 0020H to 007FH Table area referenced by the GETI instructionNote . Note The GETI instruction realizes a 1-byte instruction on behalf of an arbitrary 2-byte instruction, 3-byte instruction, or two 1-byte instructions. It is used to decrease the program steps. * Data memory * Data area Static RAM EEPROM * Peripheral hardware area *** *** *** 128 words x 4 bits (000H to 07FH) 16 words x 8 bits (400H to 41FH) 128 words x 4 bits (F80H to FFFH) 15 PD754144, 754244 Figure 5-1. Program Memory Map Address 0000H 0001H 0002H 0003H 0004H 0005H 0006H 0007H 0008H 0009H 000AH 000BH 000CH 000DH 000EH 000FH MBE RBE 0 0 MBE RBE 0 0 MBE RBE 0 0 INTT0 start address INTT0 start address INTT1/INTT2 start address INTT1/INTT2 start address INTEE start address INTEE start address (high-order 4 bits) (low-order 8 bits) (high-order 4 bits) (low-order 8 bits) (high-order 4 bits) (low-order 8 bits) GETI Branch/call Addresses Branch address of BR !addr BRCB !caddr BR BCDE BR BCXA BRA !addrNote CALL !addr CALLA !addrNote instructions MBE RBE 0 0 MBE RBE 0 0 7 MBE 6 RBE 5 0 4 0 Internal reset start address Internal reset start address INTBT start address INTBT start address INT0 start address INT0 start address 0 (high-order 4 bits) (low-order 8 bits) (high-order 4 bits) (low-order 8 bits) (high-order 4 bits) (low-order 8 bits) CALLF !faddr instruction entry address BR $addr instruction relative branch address (-15 to -1, +2 to +16) 0020H GET instruction reference table 007FH 0080H 07FFH 0800H 0FFFH Note Can be used in the MkII mode only. Remark In addition to the above, a branch can be made to an address with the low-order 8-bits only of the PC changed by means of a BR PCDE or BR PCXA instruction. 16 PD754144, 754244 Figure 5-2. Data Memory Map Data memory 000H General-purpose register area 01FH 020H Data area static RAM (128 x 4) Stack area 128 x 4 (96 x 4) (32 x 4) Memory bank 0 07FH 080H 0FFH Not incorporated 400H Data area EEPROM (16 x 8) 41FH 420H 4FFH Not incorporated 16 x 8 4 F80H Peripheral hardware area 128 x 4 15 FFFH 17 PD754144, 754244 6. EEPROM The PD754244 incorporates 16 words x 8 bit EEPROM (Electrically Erasable PROM) as well as static RAM (128 words x 4 bit) as a data memory. The EEPROM incorporated into the PD754244 has the following features. (1) Written data is retained if power is turned off. (2) 8-bit data manipulation (auto-erase/auto-write) is available by memory manipulation instruction as well as for static RAM. However available instructions are restricted. (3) It can reduce loads of software because the auto-erase and/or auto-write operation is performed by hardware. (4) Write operation control using the interrupt request The interrupt request is generated under following conditions. * Terminates write operation * Write status flag It is possible to check whether enables or disables write operation by bit manipulation instructions. 18 PD754144, 754244 7. PERIPHERAL HARDWARE FUNCTIONS 7.1 Digital Input/Output Ports The following two types of I/O ports are provided. * CMOS input (Port 7) * CMOS I/O (Ports 3, 6, 8) Total : : 4 9 : 13 Table 7-1. Types and Features of Digital Ports Port Name PORT3 PORT6 Function 4-bit I/O Operation and Features Can be set to input or output mode bit-wise. Remarks Also used as PTO0 to PTO2 pins. Also used as AVREF, INT0, PTH00, and PTH01 pins. PORT7 4-bit input 4-bit input only port On-chip pull-up resistor connection can be specified by mask option bit-wise. Also used as KR4 to KR7 pins. PORT8 1-bit I/O Can be set to input or output mode bit wise. _ 7.2 Clock Generator The clock generator provides the clock signals to the CPU and peripheral hardware. Its configuration is shown in Figures 7-1 and 7-2. The operation of the clock generator is set with the processor clock control register (PCC). The instruction execution time can be changed. * PD754144 * * * 4, 8, 16, 64 s (when the system clock fCC operates at 1.0 MHz) 0.95, 1.91, 3.81, 15.3 s (when the system clock fX operates at 4.19 MHz) 0.67, 1.33, 2.67, 10.7 s (when the system clock fX operates at 6.0 MHz) * PD754244 19 PD754144, 754244 Figure 7-1. PD754144 (RC Oscillation) Clock Generator Block Diagram * Basic interval timer (BT) * Timer counter * INT0 noise eliminator CL1 System clock oscillator 1/1~1/4096 fcc 1/2 1/4 1/16 Divider CL2 Oscillation stops Selector Divider 1/4 * CPU * INT0 noise eliminator Internal bus PCC PCC0 PCC1 4 PCC2 HALTNote PCC3 STOPNote PCC2, PCC3 clear STOP F/F Q S R R Q HALT F/F S Wait release signal from BT Reset signal Standby release signal from interrupt control circuit Note Instruction execution fcc: System clock frequency = CPU clock PCC: Processor Clock Control Register One clock cycle (tCY) of the CPU clock is equal to one machine cycle of the instruction. Remarks 1. 2. 3. 4. 20 PD754144, 754244 Figure 7-2. PD754244 (Crystal/Ceramic Oscillation) Clock Generator Block Diagram * Basic interval timer (BT) * Timer counter * INT0 noise eliminator X1 System clock oscillator 1/1~1/4096 fX 1/2 1/4 1/16 Divider X2 Oscillation stops Selector Divider 1/4 * CPU * INT0 noise eliminator Internal bus PCC PCC0 PCC1 4 PCC2 HALTNote PCC3 STOPNote PCC2, PCC3 clear STOP F/F Q S R R Q HALT F/F S Wait release signal from BT Reset signal Standby release signal from interrupt control circuit Note Instruction execution fX: System clock frequency = CPU clock PCC: Processor Clock Control Register One clock cycle (tCY) of the CPU clock is equal to one machine cycle of the instruction. Remarks 1. 2. 3. 4. 21 PD754144, 754244 7.3 Basic Interval Timer/Watchdog Timer The basic interval timer/watchdog timer has the following functions. (a) Interval timer operation to generate a reference time interrupt (b) Watchdog timer operation to detect a runaway of program and reset the CPU (c) Selects and counts the wait time when the standby mode is released (PD754244 only) Note 1 (d) Reads the contents of counting Figure 7-3. Basic Interval Timer/Watchdog Timer Block Diagram From clock generator fX/25 fX/27 MPX fX/29 fX/212 3 BT Clear Clear Basic interval timer (8-bit frequency divider) Set BT interrupt request flag Vectored interrupt IRQBT request signal Wait release signal when standby is releasedNote 1. Internal reset signal WDTM SET1Note 2 1 BTM3 BTM2 BTM1 BTM0 BTM SET1Note 2 4 8 Internal bus Notes 1. In the PD754144 (RC oscillation), the wait time cannot be specified when the standby mode is released. The oscillation stabilization wait time is negligible in the PD754144 and this device 9 returns to the normal operation mode after counting 2 /fCC (512 s: @ fCC = 1.0-MHz operation). In the PD754244 (crystal/ceramic oscillation), on the other hand, the wait time can be specified when the standby mode is released. 2. Instruction execution. 22 PD754144, 754244 7.4 Timer Counter The PD754244 incorporates three channels of timer counters. Its configuration is shown in Figures 7-4 to 7-6. The timer counter has the following functions. (a) Programmable interval timer operation (b) Square wave output of any frequency to PTO0-PTO2 pins (c) Count value read function The timer counter can operate in the following four modes as set by the mode register. Table 7-2. Mode List Mode 8-bit timer counter mode PWM pulse generator mode 16-bit timer counter mode Carrier generator mode x x x x Channel Channel 0 Channel 1 Channel 2 TM11 0 0 1 0 TM10 0 0 0 0 TM21 0 0 1 1 TM20 0 1 0 1 Remark : x: Available Not available 23 24 8 SET1Note - TM06 TM05 TM04 TM03 TM02 fx/24 From clock fx/26 generator fx/28 fx/210 MPX Figure 7-4. Timer Counter (Channel 0) Block Diagram Internal bus 8 TM0 0 0 8 TMOD0 Modulo register (8) 8 Match TOE0 T0 enable flag PORT3.0 P30 Output latch PMGA bit 0 Port 3 input/output mode Comparator (8) TOUT F/F Reset P30/PTO0 Output buffer 8 T0 CP Count register (8) Clear INTT0 IRQT0 set signal Timer operation start RESET IRQT0 clear signal Note Instruction execution Caution When setting data to TM0, be sure to set bits 0 and 1 to 0. PD754144, 754244 Figure 7-5. Timer Counter (Channel 1) Block Diagram Internal bus 8 - SETNote TM1 TOE1 8 TMOD1 Decoder Modulo register (8) 8 Comparator (8) Match TOUT F/F Reset T1 P31/PTO1 Output buffer T1 enable flag PORT3.1 P31 Output latch PMGA bit 1 Port 3 input/output mode TM16 TM15 TM14 TM13 TM12 TM11 TM10 Timer counter (channel 2) output fx/25 fx/26 fx/28 fx/210 fx/212 8 Count register (8) Clear From clock generator MPX CP RESET Timer operation start 16 bit timer counter mode IRQT1 clear signal Selector Timer counter (channel 2) match signal (When 16-bit timer counter mode) Timer counter (channel 2) reload signal INTT1 IRQT1 set signal PD754144, 754244 Timer counter (channel 2) comparator (When 16-bit timer counter mode) Note Instruction execution 25 Selector From clock generator fx fx/2 fx/24 fx/26 fx/28 fx/210 8 T2 MPX CP Count register (8) Clear Reset Overflow Carrier generator mode Selector 26 8 - Figure 7-6. Timer Counter (Channel 2) Block Diagram Internal bus SET Note TM2 8 TMODH 8 8 MPX (8) 8 Comparator (8) 8 TMOD2 0 - - 8 - TC2 TOE2 REMC NRZB NRZ Reload PORT3.2 Output latch PMGA bit 2 TM26 TM25 TM24 TM23 TM22 TM21 TM20 High-level period setting modulo register (8) Modulo register (8) Port 3 input/output mode Decoder Match TOUT F/F P32/PTO2 Output buffer Timer counter (channel 1) clock input 16-bit timer counter mode Timer operation start INTT2 IRQT2 set signal IRQT2 clear signal RESET Timer counter (channel 1) clear signal (When 16-bit timer mode) Timer counter (channel 1) match signal (When 16-bit timer counter mode) Timer counter (channel 1) match signal (When Carrier generator mode) Note Instruction execution Caution When setting data to TC2, be sure to set bit 7 to 0. PD754144, 754244 PD754144, 754244 7.5 Programmable Threshold Port (Analog Input Port) The PD754244 provides analog input pins (PTH00, PTH01) whose threshold voltage (reference voltage) is selectable within sixteen steps. The following operations can be performed with these analog input pins. (1) (2) Comparator operation 4-bit resolution A/D converter operation (controlled by software) Do not specify an on-chip pull-up resistor connection for Port 6 when using the programmable threshold port. Figure 7-7. Programmable Threshold Port Block Diagram Caution PTH0 PTH00 + - Input buffer Programmable threshold port input latch (2) PTH01 + - Input buffer Standby mode signal AVREF PTHM7 1 R 2 PTHM6 PTHM5 R PTHM4 R MPX VREF 8 PTHM3 PTHM2 PTHM1 1 R 2 PTHM0 PTHM Internal bus Operate/stop 27 PD754144, 754244 7.6 Bit Sequential Buffer ....... 16 Bits The bit sequential buffer (BSB) is a special data memory for bit manipulation and the bit manipulation can be easily performed by changing the address specification and bit specification in sequence, therefore it is useful when processing large data bit-wise. Figure 7-8. Bit Sequential Buffer Format Address Bit Symbol 3 FC3H 2 1 0 3 FC2H 2 1 0 3 FC1H 2 1 0 3 FC0H 2 1 0 BSB3 BSB2 BSB1 BSB0 L register L = FH L = CH L = BH L = 8H L = 7H DECS L L = 4H L = 3H L = 0H INCS L Remarks 1. 2. In the pmem.@L addressing, the specified bit moves corresponding to the L register. In the pmem.@L addressing, the BSB can be manipulated regardless of MBE/MSB specification. 28 PD754144, 754244 8. INTERRUPT FUNCTION AND TEST FUNCTION Figure 8-1 shows the interrupt control circuit. Each hardware device is mapped in the data memory space. The interrupt control circuit of the PD754244 has the following functions. (1) Interrupt function * Vectored interrupt function for hardware control, enabling/disabling the interrupt acknowledgement by the interrupt enable flag (IExxx) and interrupt master enable flag (IME). * Can set any interrupt start address. * Multiple interrupts wherein the order of priority can be specified by the interrupt priority select register (IPS). * Test function of interrupt request flag (IRQxxx). An interrupt generated can be checked by software. * Release the standby mode. A release interrupt can be selected by the interrupt enable flag. (2) Test function * Test request flag (IRQ2) generation can be checked by software. * Release the standby mode. The test source to be released can be selected by the test enable flag. 29 Selector 30 2 IM2 4 IM0 INTBT INT0/P61 Note1 Figure 8-1. Interrupt Control Circuit Block Diagram Internal bus Interrupt enable flag (IExxx) IME IPS IST1 IST0 Decoder VRQn IRQBT IRQ0 IRQT0 IRQT1 IRQT2 IRQEE IRQ2 Priority control ciricuit Vector table address generator Edge detector INTT0 INTT1 INTT2 INTEE KR4/P70 KR7/P73 Falling edge detectorNote2 Key return reset circuit IM2 Standby release signal PD754144, 754244 Notes 1. 2. Noise eliminator (Standby release is disable when noise eliminator is selected.) The INT2 pin is not provided. Interrupt request flag (IRQ2) is set at the KRn pin falling edge when IM20 = 1 and IM21 = 0. PD754144, 754244 9. STANDBY FUNCTION In order to reduce power dissipation while a program is in a standby mode, two types of standby modes (STOP mode and HALT mode) are provided for the PD754244. Table 9-1. Operation Status in Standby Mode Item Set instruction Operation status Clock generator Mode STOP Mode STOP instruction Operation stops. HALT Mode HALT instruction Only the CPU clock halts (oscillation continues). Operable BT mode: The IRQBT is set in the basic time interval. WT mode: Reset is generated by the BT overflow. Operable. Basic interval timer/ watchdog timer Operation stops. Timer External interrupt Operation stops. INT0 is not operable. Note INT2 is operable during KRn falling period only. CPU Release signal The operation stops. * Reset signal * Interrupt request signal sent from interrupt enabled peripheral hardware * System reset signal (key return reset) generated by KRn falling edge when the KRREN pin = 1 * Reset signal * Interrupt request signal sent from interrupt enabled peripheral hardware Note Can operate only when the noise eliminator is not used (IM02 = 1) by bit 2 of the edge detection mode register (IM0). 31 PD754144, 754244 10. RESET FUNCTION 10.1 Configuration and Operation Status of RESET Function There are three kinds of reset input: the external reset signal (RESET), the reset signal sent from the basic interval/watchdog timer, and the reset signal generated by a falling edge signal from KRn in the STOP mode. When any of these reset signals is input, an internal reset signal is generated. The configuration is shown in Figure 10-1. Figure 10-1. Configuration of Reset Function VDD Mask option RESET Internal reset signal Output buffer Watchdog timer overflow S R Instruction KRREN S R Q R S Instruction STOP mode VDD One-shot pulse generator Q WDF Q KRF Interrupt Falling edge detector Mask option P70/KR4 P71/KR5 P72/KR6 P73/KR7 Internal bus 32 PD754144, 754244 Each hardware is initialized by the RESET signal generation as listed in Table 10-1. Figure 10-2 shows the timing chart of the reset operation. Figure 10-2. Reset Operation by RESET Signal Generation WaitNote RESET signal generated Operation mode or standby mode HALT mode Internal reset operation Operation mode Note In the PD754144, the wait time is fixed to 56/fcc (56s: @ 1.0-MHz operation). In the PD754244, the wait time can be selected from the following two time settings by means of the mask option. 17 2 /fx (21.8 ms : @ 6.0-MHz operation, 31.3 ms: @ 4.19-MHz operation) 15 2 /fx (5.46 ms : @ 6.0-MHz operation, 7.81 ms: @ 4.19-MHz operation) 33 PD754144, 754244 Table 10-1. Hardware Status After Reset (1/3) RESET signal generation in the standby mode Sets the low-order 4 bits of program memory's address 0000H to the PC11-PC8 and the contents of address 0001H to the PC7-PC0. Held 0 0 Sets the bit 6 of program memory's address 0000H to the RBE and bit 7 to the MBE. Undefined 1000B Held Held Note 1 Hardware Program counter (PC) RESET signal generation in operation Sets the low-order 4 bits of program memory's address 0000H to the PC11-PC8 and the contents of address 0001H to the PC7-PC0. Undefined 0 0 Sets the bit 6 of program memory's address 0000H to the RBE and bit 7 to the MBE. Undefined 1000B Undefined HeldNote 2 0 Undefined 0, 0 Undefined 0 0 0 FFH 0 0, 0 0 FFH 0 0, 0 0 FFH FFH PSW Carry flag (CY) Skip flag (SK0 to SK2) Interrupt status flag (IST0, IST1) Bank enable flag (MBE, RBE) Stack pointer (SP) Stack bank select register (SBS) Data memory (RAM) Data memory (EEPROM) EEPROM write control register (EWC) General-purpose register (X, A, H, L, D, E, B, C) Bank select register (MBS, RBS) Basic interval timer/watchdog timer Timer counter (channel 0) Counter (BT) Mode register (BTM) Watchdog timer enable flag (WDTM) Counter (T0) Modulo register (TMOD0) Mode register (TM0) TOE0, TOUT F/F Timer counter (channel 1) Counter (T1) Modulo register (TMOD1) Mode register (TM1) TOE1, TOUT F/F Timer counter (channel 2) Counter (T2) Modulo register (TMOD2) High-level period setting modulo register (TMOD2H) Mode register (TM2) TOE2, TOUT F/F REMC, NRZ, NRZB 0 Held 0, 0 Undefined 0 0 0 FFH 0 0, 0 0 FFH 0 0, 0 0 FFH FFH 0 0, 0 0, 0, 0 0 0, 0 0, 0, 0 Notes 1. 2. Undefined if STOP mode is entered during an EEPROM write operation. Also undefined if HALT mode is entered during a write operation and a RESET signal is input during a write operation. If a RESET signal is input during an EEPROM write operation, the data at that address is undefined. 34 PD754144, 754244 Table 10-1. Hardware Status After Reset (2/3) RESET signal generation in the standby mode 00H 0 Reset (0) 0 0 0, 0 Off Cleared (0) 0 0 Held RESET signal generation in operation 00H 0 Reset (0) 0 0 0, 0 Off Cleared (0) 0 0 Undefined Hardware Programmable threshold port mode register (PTHM) Clock generator Interrupt function Processor clock control register (PCC) Interrupt request flag (IRQxxx) Interrupt enable flag (IExxx) Interrupt priority selection register (IPS) INT0, 2 mode registers (IM0, IM2) Digital port Output buffer Output latch I/O mode registers (PMGA, C) Pull-up resistor setting register (POGA, B) Bit sequential buffer (BSB0-BSB3) Table 10-1. Hardware Status After Reset (3/3) RESET signal generation by key return reset Hold the previous status 1 RESET signal generation in the standby mode 0 0 RESET signal generation by WDT during operation 1 Hold the previous status RESET signal generation during operation 0 0 Hardware Watchdog flag (WDF) Key return flag (KRF) 35 PD754144, 754244 10.2 Watchdog Flag (WDF), Key Return Flag (KRF) The WDF is cleared by a watchdog timer overflow signal, and the KRF is set by a reset signal generated by the KRn pins. As a result, by checking the contents of WDF and KRF, it is possible to know what kind of reset signal is generated. As the WDF and KRF are cleared only by external signal or instruction execution, if once these flags are set, they are not cleared until an external signal is generated or a clear instruction is executed. Check and clear the contents of WDF and KRF after reset start operation by executing SKTCLR instruction and so on. Table 10-2 lists the contents of WDF and KRF corresponding to each signal. Figure 10-3 shows the WDF operation in generating each signal, and Figure 10-4 shows the KRF operation in generating each signal. Table 10-2. WDF and KRF Contents Correspond to Each Signal External RESET signal generation Reset signal Reset signal generation by watch- generation by the dog timer overflow KRn input 1 Hold Hold 1 WDF clear instruction execution 0 Hold KRF clear instruction execution Hold 0 Hardware Watchdog flag (WDF) Key return flag (KRF) 0 0 Figure 10-3. WDF Operation in Generating Each Signal Reset signal generation by watchdog timer overflow External RESET signal generation Reset signal generation by watchdog timer overflow WDF clear instruction execution WDF External RESET Operation mode Operation mode HALT mode Operation mode HALT mode Operation mode HALT mode Operation mode Internal reset operation Internal reset operation Internal reset operation 36 PD754144, 754244 Figure 10-4. KRF Operation in Generating Each Signal Reset signal generation by the KRn input STOP instruction execution External RESET signal generation Reset signal generation by the KRn input STOP instruction execution KRF clear instruction execution KRF External RESET Operation mode Operation mode STOP mode HALT mode Operation mode HALT mode Operation mode STOP mode HALT mode Operation mode Internal reset operation Internal reset operation Internal reset operation 37 PD754144, 754244 11. MASK OPTION The PD754244 has the following mask options: * Mask option of P70/KR4 to P73/KR7 On-chip pull-up resistor connection can be specified for these pins. (1) Do not connect an on-chip pull-up resistor (2) Connect the 100-k (typ.) pull-up resistor bit-wise * Mask option of RESET pin On-chip pull-up resistor connection can be specified for this pin. (1) Do not connect an on-chip pull-up resistor (2) Connect the 100-k (typ.) pull-up resistor * Standby function mask option (PD754244 only) Note The wait time when the RESET signal is input can be selected. (1) 217 /fX (21.8 ms: @ fX = 6.0-MHz operation, 31.3 ms: @ fX = 4.19-MHz operation) (2) 215 /fX (5.46 ms: @ fX = 6.0-MHz operation, 7.81 ms: @ fX = 4.19-MHz operation) Note This mask option is not provided for the PD754144, and its wait time is fixed to 56/fCC (56 s: @ fCC = 1.0-MHz operation). 38 PD754144, 754244 12. INSTRUCTION SETS (1) Expression formats and description methods of operands The operand is described in the operand column of each instruction in accordance with the description method for the operand expression format of the instruction. For details, refer to "RA75X ASSEMBLER PACKAGE USERS' MANUAL -- LANGUAGE (EEU-1367)". If there are several elements, one of them is selected. Capital letters and the + and - symbols are key words and are described as they are. For immediate data, appropriate numbers and labels are described. Instead of the labels such as mem, fmem, pmem, and bit, the symbols of the registers can be described. However, there are restrictions in the labels that can be described for fmem and pmem. For details, refer to "PD754144, 754244 user's manual (U10676E)". Expression format reg reg1 rp rp1 rp2 rp' rp'1 rpa rpa1 n4 n8 mem bit fmem pmem addr addr1 caddr faddr taddr PORTn IExxx RBn MBn X, A, B, C, D, E, H, L X, B, C, D, E, H, L XA, BC, BC, XA, BC, BC, DE, DE BC, DE, DE, HL HL DE, HL, XA', BC', DE', HL' HL, XA', BC', DE', HL' Description method HL, HL+, HL-, DE, DL DE, DL 4-bit immediate data or label 8-bit immediate data or label 8-bit immediate data or labelNote 2-bit immediate data or label FB0H-FBFH, FF0H-FFFH immediate data or label FC0H-FFFH immediate data or label 000H-FFFH immediate data or label 000H-FFFH immediate data or label 12-bit immediate data or label 11-bit immediate data or label 20H-7FH immediate data (where bit 0 = 0) or label PORT3, 6, 7, 8 IEBT, IET0-IET2, IE0, IE2, IEEE RB0-RB3 MB0, MB4, MB15 Note mem can be only used for even address in 8-bit data processing. 39 PD754144, 754244 (2) Legend in explanation of operation A B C D E H L X XA BC DE HL XA' BC' DE' HL' PC SP CY PSW MBE RBE PORTn IME IPS IExxx RBS MBS PCC . (xx) xxH : A register, 4-bit accumulator : B register : C register : D register : E register : H register : L register : X register : XA register pair; 8-bit accumulator : BC register pair : DE register pair : HL register pair : XA' extended register pair : BC' extended register pair : DE' extended register pair : HL' extended register pair : Program counter : Stack pointer : Carry flag, bit accumulator : Program status word : Memory bank enable flag : Register bank enable flag : Port n (n = 3, 6, 7, 8) : Interrupt master enable flag : Interrupt priority selection register : Interrupt enable flag : Register bank selection register : Memory bank selection register : Processor clock control register : Separation between address and bit : The contents addressed by xx : Hexadecimal data 40 PD754144, 754244 (3) Explanation of symbols under addressing area column *1 MB = MBE*MBS (MBS = 0, 4, 15) MB = 0 MBE = 0 : MB = 0 (000H to 07FH) MB = 15 (F80H to FFFH) MBE = 1 : MB = MBS (MBS = 0, 4, 15) MB = 15, fmem = FB0H to FBFH, FF0H to FFFH MB = 15, pmem = FC0H to FFFH addr = 000H to FFFH addr = (Current PC) - 15 to (Current PC) - 1 (Current PC) + 2 to (Current PC) + 16 *2 *3 Data memory addressing *4 *5 *6 *7 addr1 = (Current PC) - 15 to (Current PC) - 1 (Current PC) + 2 to (Current PC) + 16 *8 *9 *10 *11 caddr = 000H to FFFH faddr = 0000H to 07FFH taddr = 0020H to 007FH addr1 = 000H to FFFH Program memory addressing Remarks 1. 2. 3. 4. MB indicates memory bank that can be accessed. In *2, MB = 0 independently of how MBE and MBS are set. In *4 and *5, MB = 15 independently of how MBE and MBS are set. *6 to *11 indicate the areas that can be addressed. (4) Explanation of number of machine cycles column S denotes the number of machine cycles required by skip operation when a skip instruction is executed. The value of S varies as follows. * When no skip is made: S = 0 * When the skipped instruction is a 1- or 2-byte instruction: S = 1 * When the skipped instruction is a 3-byte instruction Note: S = 2 Note 3-byte instruction: BR !addr, BRA !addr1, CALL !addr, or CALLA !addr1 instruction Caution The GETI instruction is skipped in one machine cycle. One machine cycle is equal to one cycle of CPU clock (= tCY); time can be selected from among four types by setting PCC. 41 PD754144, 754244 Number of machine cycles 1 2 2 2 2 1 2+S 2+S 1 2 1 2 2 2 2 2 2 2 2 2 1 2+S 2+S 1 2 2 2 1 2 3 3 3 3 A n4 reg1 n4 XA n8 HL n8 rp2 n8 A (HL) A (HL), then L L+1 A (HL), then L L-1 A (rpa1) XA (HL) (HL) A (HL) XA A (mem) XA (mem) (mem) A (mem) XA A reg XA rp' reg1 A rp'1 XA A (HL) A (HL), then L L+1 A (HL), then L L-1 A (rpa1) XA (HL) A (mem) XA (mem) A reg1 XA rp' XA (PC11-8+DE)ROM XA (PC11-8+XA)ROM XA (BCDE)ROMNote XA (BCXA)ROMNote *6 *6 *1 *1 *1 *2 *1 *3 *3 L=0 L = FH *1 *1 *1 *2 *1 *1 *1 *3 *3 *3 *3 L=0 L = FH String effect A String effect B Instruction group Transfer instruction Mnemonic Operand Number of bytes 1 2 2 2 2 1 1 1 1 2 1 2 2 2 2 2 2 2 2 2 1 1 1 1 2 2 2 1 2 1 1 1 1 Operation Addressing area Skip condition MOV A, #n4 reg1, #n4 XA, #n8 HL, #n8 rp2, #n8 A, @HL A, @HL+ A, @HL- A, @rpa1 XA, @HL @HL, A @HL, XA A, mem XA, mem mem, A mem, XA A, reg XA, rp' reg1, A rp'1, XA String effect A XCH A, @HL A, @HL+ A, @HL- A, @rpa1 XA, @HL A, mem XA, mem A, reg1 XA, rp' Table reference instructions MOVT XA, @PCDE XA, @PCXA XA, @BCDE XA, @BCXA Note Set "0" in register B. 42 PD754144, 754244 Number of machine cycles 2 2 2 2 2 2 1+S 2+S 1+S 2+S 2+S 1 2 2 1+S 2+S 2+S 1 2 2 2 1 2 2 2 1 2 2 2 1 2 2 1 2 CY (fmem.bit) CY (pmem7-2+L3-2.bit(L1-0)) CY (H+mem3-0.bit) (fmem.bit) CY (pmem7-2+L3-2.bit(L1-0)) CY (H+mem3-0.bit) CY A A+n4 XA XA+n8 A A+(HL) XA XA+rp' rp'1 rp'1+XA A, CY A+(HL)+CY XA, CY XA+rp'+CY rp'1, CY rp'1+XA+CY A A-(HL) XA XA-rp' rp'1 rp'1-XA A, CY A-(HL)-CY XA, CY XA-rp'-CY rp'1, CY rp'1-XA-CY A A n4 A A (HL) XA XA rp' rp'1 rp'1 XA A A n4 A A (HL) XA XA rp' rp'1 rp'1 XA A A v n4 A A v (HL) XA XA v rp' rp'1 rp'1 v XA CY A0, A3 CY, An-1 An AA *1 *1 *1 *1 *1 borrow borrow borrow *1 *1 Instruction group Bit transfer instructions Mnemonic Operand Number of bytes 2 2 2 2 2 2 1 2 1 2 2 1 2 2 1 2 2 1 2 2 2 1 2 2 2 1 2 2 2 1 2 2 1 2 Operation Addressing area *4 *5 *1 *4 *5 *1 Skip condition MOV1 CY, fmem.bit CY, pmem.@L CY, @H+mem.bit fmem.bit, CY pmem.@L, CY @H+mem.bit, CY Operation instructions ADDS A, #n4 XA, #n8 A, @HL XA, rp' rp'1, XA carry carry carry carry carry ADDC A, @HL XA, rp' rp'1, XA SUBS A, @HL XA, rp' rp'1, XA SUBC A, @HL XA, rp' rp'1, XA AND A, #n4 A, @HL XA, rp' rp'1, XA OR A, #n4 A, @HL XA, rp' rp'1, XA XOR A, #n4 A, @HL XA, rp' rp'1, XA Accumulator manipulation instructions RORC NOT A A 43 PD754144, 754244 Number of machine cycles 1+S 1+S 2+S 2+S 1+S 2+S 2+S 2+S 1+S 2+S 2+S 2+S 1 1 1+S 1 2 2 2 2 2 2 2 2 2+S 2+S 2+S 2+S 2+S 2+S 2+S 2+S reg reg+1 rp1 rp1+1 (HL) (HL)+1 (mem) (mem)+1 reg reg-1 rp' rp'-1 Skip if reg = n4 Skip if (HL) = n4 Skip if A = (HL) Skip if XA = (HL) Skip if A = reg Skip if XA = rp' CY 1 CY 0 Skip if CY = 1 CY CY (mem.bit) 1 (fmem.bit) 1 (pmem7-2+L3-2.bit(L1-0)) 1 (H+mem3-0.bit) 1 (mem.bit) 0 (fmem.bit) 0 (pmem7-2+L3-2.bit(L1-0)) 0 (H+mem3-0.bit) 0 Skip if (mem.bit)=1 Skip if (fmem.bit)=1 Skip if (pmem7-2+L3-2.bit(L1-0))=1 Skip if (H+mem3-0.bit)=1 Skip if (mem.bit)=0 Skip if (fmem.bit)=0 Skip if (pmem7-2+L3-2.bit(L1-0))=0 Skip if (H+mem3-0.bit)=0 *3 *4 *5 *1 *3 *4 *5 *1 *3 *4 *5 *1 *3 *4 *5 *1 (mem.bit)=1 (fmem.bit)=1 (pmem.@L)=1 (@H+mem.bit)=1 (mem.bit)=0 (fmem.bit)=0 (pmem.@L)=0 (@H+mem.bit)=0 CY=1 *1 *1 *1 *1 *3 Instruction group Increment and Decrement instructions Mnemonic Operand Number of bytes 1 1 2 2 1 2 2 1 2 2 2 2 1 1 1 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 Operation Addressing area Skip condition INCS reg rp1 @HL mem reg=0 rp1=00H (HL)=0 (mem)=0 reg=FH rp'=FFH reg=n4 (HL) = n4 A = (HL) XA = (HL) A=reg XA=rp' DECS reg rp' Comparison instruction SKE reg, #n4 @HL, #n4 A, @HL XA, @HL A, reg XA, rp' Carry flag manipulation instruction SET1 CLR1 SKT NOT1 CY CY CY CY mem.bit fmem.bit pmem.@L @H+mem.bit Memory bit manipulation instructions SET1 CLR1 mem.bit fmem.bit pmem.@L @H+mem.bit SKT mem.bit fmem.bit pmem.@L @H+mem.bit SKF mem.bit fmem.bit pmem.@L @H+mem.bit 44 PD754144, 754244 Number of machine cycles 2+S 2+S 2+S 2 2 2 2 2 2 2 2 2 - Instruction group Memory bit manipulation instructions Mnemonic Operand Number of bytes 2 2 2 2 2 2 2 2 2 2 2 2 - Operation Addressing area *4 *5 *1 *4 *5 *1 *4 *5 *1 *4 *5 *1 *6 Skip condition SKTCLR fmem.bit pmem.@L @H+mem.bit Skip if (fmem.bit)=1 and clear Skip if (pmem7-2+L3-2.bit(L1-0))=1 and clear Skip if (H+mem3-0.bit)=1 and clear CY CY (fmem.bit) CY CY (pmem7-2+L3-2.bit(L1-0)) CY CY (H+mem3-0.bit) CY CY (fmem.bit) CY CY (pmem7-2+L3-2.bit(L1-0)) CY CY (H+mem3-0.bit) CY CY v (fmem.bit) CY CY v (pmem7-2+L3-2.bit(L1-0)) CY CY v (H+mem3-0.bit) PC11-0 addr Select appropriate instruction among BR !addr BRCB !caddr, and BR $addr according to the assembler being used. PC11-0 addr Select appropriate instruction among BR !addr BRA !addr1, BRCB !caddr and BR $addr1 according to the assembler being used. PC11-0 addr PC11-0 addr PC11-0 addr1 PC11-0 PC11-8+DE PC11-0 PC11-8+XA PC11-0 BCDENote 2 PC11-0 BCXANote 2 PC11-0 addr1 PC11-0 caddr11-0 (fmem.bit)=1 (pmem.@L)=1 (@H+mem.bit)=1 AND1 CY, fmem.bit CY, pmem.@L CY, @H+mem.bit OR1 CY, fmem.bit CY, pmem.@L CY, @H+mem.bit XOR1 CY, fmem.bit CY, pmem.@L CY, @H+mem.bit Branch instructions BRNote 1 addr addr1 - - *11 ! addr $addr $addr1 PCDE PCXA BCDE BCXA BRANote 1 BRCB !addr1 !caddr 3 1 1 2 2 2 2 3 2 3 2 2 3 3 3 3 3 2 *6 *7 *6 *6 *11 *8 Notes 1. 2. The above operations in the double boxes can be performed only in the Mk II mode. "0" must be set to B register. 45 PD754144, 754244 Number of machine cycles 3 Instruction group Subroutine stack control instructions Mnemonic Operand Number of bytes 3 Operation (SP-2) x, x, MBE, RBE (SP-6) (SP-3) (SP-4) PC11-0 (SP-5) 0, 0, 0, 0 PC11-0 addr1, SP SP-6 (SP-3) MBE, RBE, 0, 0 (SP-4) (SP-1) (SP-2) PC11-0 PC11-0 addr, SP SP-4 (SP-2) x, x, MBE, RBE (SP-6) (SP-3) (SP-4) PC11-0 (SP-5) 0, 0, 0, 0 PC11-0 addr, SP SP-6 (SP-3) MBE, RBE, 0, 0 (SP-4) (SP-1) (SP-2) PC11-0 PC11-0 0+faddr, SP SP-4 (SP-2) x, x, MBE, RBE (SP-6) (SP-3) (SP-4) PC11-0 (SP-5) 0, 0, 0, 0 PC11-0 0+faddr, SP SP-6 PC11-0 (SP) (SP+3) (SP+2) MBE, RBE, 0, 0 (SP+1), SP SP+4 x, x, MBE, RBE (SP+4) 0, 0, 0, 0, (SP+1) PC11-0 (SP) (SP+3) (SP+2), SP SP+6 Addressing area *11 Skip condition CALLANote !addr1 CALLNote !addr 3 3 *6 4 CALLFNote !faddr 2 2 *9 3 RETNote 1 3 RETSNote 1 3+S MBE, RBE, 0, 0 (SP+1) PC11-0 (SP) (SP+3) (SP+2) SP SP+4 then skip unconditionally 0, 0, 0, 0 (SP+1) PC11-0 (SP) (SP+3) (SP+2) x, x, MBE, RBE (SP+4) SP SP+6 then skip unconditionally Unconditional RETINote 1 3 MBE, RBE, 0, 0 (SP+1) PC11-0 (SP) (SP+3) (SP+2) PSW (SP+4) (SP+5), SP SP+6 0, 0, 0, 0 (SP+1) PC11-0 (SP) (SP+3) (SP+2) PSW (SP+4) (SP+5), SP SP+6 PUSH rp BS 1 2 1 2 1 2 1 2 (SP-1) (SP-2) rp, SP SP-2 (SP-1) MBS, (SP-2) RBS, SP SP-2 rp (SP+1) (SP), SP SP+2 MBS (SP+1), RBS (SP), SP SP+2 POP rp BS Note The above operations in the double boxes can be performed only in the Mk II mode. The other operations can be performed only in the Mk I mode. 46 PD754144, 754244 Number of machine cycles 2 2 2 2 2 2 2 2 1 2 2 3 IME (IPS.3) 1 IExxx 1 IME (IPS.3) 0 IExxx 0 A PORTn PORTn A Set HALT Mode (PCC.2 1) Set STOP Mode (PCC.3 1) No Operation RBS n MBS n (n = 0-3) (n = 0, 4, 15) *10 ------------- Instruction group Interrupt control instructions Mnemonic Operand Number of bytes 2 Operation Addressing area Skip condition EI IExxx DI IExxx 2 2 2 2 2 2 2 1 Input/output instructions INNote 1 OUT Note 1 A, PORTn PORTn, A (n = 3, 6, 7, 8) (n = 3, 6, 8) CPU control instructions HALT STOP NOP Special instructions SEL RBn MBn 2 2 1 GETINotes 2, 3 taddr * When TBR instruction PC11-0 (taddr) 3-0 + (taddr+1) ---------------------------------- * When TCALL instruction (SP-4) (SP-1) (SP-2) PC11-0 (SP-3) MBE, RBE, 0, 0 PC11-0 (taddr) 3-0 + (taddr+1) SP SP-4 ---------------------------------- ------------- * When instruction other than TBR and TCALL instructions (taddr) (taddr+1) instruction is executed. 3 * When TBR instruction PC11-0 (taddr) 3-0 + (taddr+1) * When TCALL instruction (SP-6) (SP-3) (SP-4) PC11-0 (SP-5) 0, 0, 0, 0 (SP-2) x, x, MBE, RBE PC11-0 (taddr) 3-0 + (taddr+1) SP SP-6 *10 Depending on the reference instruction ------------------------------------- --- ------------- 4 ------------------------------------- --- ------------- 3 * When instruction other than TBR and TCALL instructions (taddr) (taddr+1) instruction is executed. Depending on the reference instruction Notes 1. 2. 3. While the IN instruction and OUT instruction are being executed, MBE must be set to 0, or MBE must be set to 1 and MBS must be set to 15. The TBR and TCALL instructions are the table definition assembler pseudo instructions of the GETI instruction. The above operations in the double boxes can be performed only in the Mk II mode. The other operations can be performed only in the Mk I mode. 47 PD754144, 754244 13. ELECTRICAL SPECIFICATIONS 13.1 PD754144 Absolute Maximum Ratings (TA = 25C) Parameter Power supply voltage Input voltage Output voltage Output current, high Symbol VDD VI VO IOH Per pin P30, P31, P33, P60 to P63, P80 P32 For all pins Output current, low IOL Per pin For all pins Operating ambient temperature Storage temperature TA Test Conditions Ratings -0.3 to +7.0 -0.3 to VDD + 0.3 -0.3 to VDD + 0.3 -10 -20 -30 20 90 -40 to +85 Unit V V V mA mA mA mA mA C C Tstg -65 to +150 Caution If any of the parameters exceeds the absolute maximum ratings, even momentarily, the quality of the product may be impaired. The absolute maximum ratings are values that may physically damage the products. Be sure to use the products within the ratings. Capacitance (TA = 25C, VDD = 0 V) Parameter Input capacitance Output capacitance I/O capacitance Symbol CIN COUT CIO f = 1 MHz Unmeasured pins returned to 0 V Test Conditions MIN. TYP. MAX. 15 15 15 Unit pF pF pF 48 PD754144, 754244 * PD754144 System Clock Oscillator Characteristics (TA = -40 to +85 C, VDD = 1.8 to 6.0 V) Resonator RC oscillator CL1 CL2 Recommended Constant Parameter Oscillation frequency (fcc) Note Testing Conditions MIN. 0.4 TYP. MAX. 2.0 Unit MHz * Note Only the oscillator characteristics are shown. For the instruction execution time and oscillation frequency characteristics, refer to AC Characteristics. Caution When using the oscillation circuit of the system clock, wire the portion enclosed in dotted lines in the figures as follows to avoid adverse influences on the wiring capacitance: * Keep the wire length as short as possible. * Do not cross other signal lines. * Do not route the wiring in the vicinity of lines though which a high fluctuating current flows. * Always keep the ground point of the capacitor of the oscillation circuit as the same potential as VSS. * Do not connect the power source pattern through which a high current flows. * Do not extract signals from the oscillation circuit. 49 PD754144, 754244 * PD754144 DC Characteristics (TA = -40 to +85C, VDD = 1.8 to 6.0 V) Parameter High-level output current Symbol IOH Per pin Conditions P30, P31, P33, P60 to P63, P80 P32, VDD = 3.0 V, VOH = VDD - 2.0 V Total of all pins Low-level output current High-level input voltage VIH2 Ports 6 to 8, KRREN, RESET Low-level input voltage VIL2 Ports 6 to 8, KRREN, RESET High-level output voltage Low-level output voltage VOL VOH VIL1 Port 3 VIH1 IOL Per pin Total of all pins Port 3 2.7 V VDD 6.0 V 1.8 V VDD < 2.7 V 2.7 V VDD 6.0 V 1.8 V VDD < 2.7 V 2.7 V VDD 6.0 V 1.8 V VDD < 2.7 V 2.7 V VDD 6.0 V 1.8 V VDD < 2.7 V 0.7VDD 0.9VDD 0.8VDD 0.9VDD 0 0 0 0 VDD - 1.0 VDD - 0.5 0.6 2.0 0.4 -20 15 45 VDD VDD VDD VDD 0.3VDD 0.1VDD 0.2VDD 0.1VDD mA mA mA V V V V V V V V V V V V -7 -15 mA MIN. TYP. MAX. -5 Unit mA VDD = 4.5 to 6.0 V, IOH = -1.0 mA VDD = 1.8 to 6.0 V, IOH = -100 A VDD = 4.5 to 6.0 V Port 3, IOL = 15 mA Ports 6, 8, IOL = 1.6 mA VDD = 1.8 to 6.0 V, IOH = 400 A 0.5 3.0 V High-level input leakage current Low-level input leakage current High-level output leakage current Low-level output leakage current On-chip pull-up resistance ILIH VIN = VDD A ILIL VIN = 0 V -3.0 A ILOH VOUT = VDD 3.0 A ILOL VOUT = 0 V -3.0 A RL1 RL2 VIN = 0 V Ports 3, 6, 8 Port 7, RESET (mask option) 50 50 100 100 200 200 k k 50 PD754144, 754244 * PD754144 DC Characteristics (TA = -40 to +85C, VDD = 1.8 to 6.0 V) Parameter Power supply current Note 1 Symbol IDD1 1.0-MHz RC oscillation IDD2 R = 22 k C = 22 pF IDD1 1.0-MHz RC oscillation IDD2 R = 5.1 k C = 120 pF IDD3 STOP mode Conditions VDD = 5.0 V 10% VDD = 3.0 V 10% HALT mode Note 2 Note 3 MIN. TYP. 0.7 0.3 0.5 0.25 1.15 0.55 0.95 0.5 MAX. 2.1 1.0 1.8 0.9 3.5 1.6 2.8 1.5 5 Unit mA mA mA mA mA mA mA mA VDD = 5.0 V 10% VDD = 3.0 V 10% Note 2 Note 3 VDD = 5.0 V 10% VDD = 3.0 V 10% HALT mode VDD = 5.0 V 10% VDD = 3.0 V 10% VDD = 1.8 to 6.0 V TA = 25C VDD = 3.0 V 10% TA = -40 to +40C 0.1 0.1 A A A A 1 3 1 Notes 1. 2. 3. The current flowing through the on-chip pull-up resistor, the current during EEPROM writing time, and the current when the program threshold port (PTH) is operating are not included. When the device is operated in the high-speed mode by setting the processor clock control register (PCC) to 0011H. When the device is operated in the low-speed mode by setting PCC to 0000H. 51 PD754144, 754244 * PD754144 AC Characteristics (TA = -40 to +85C, VDD = 1.8 to 6.0 V) Parameter CPU clock cycle time Note1 Symbol tCY Test Conditions MIN. 2.0 TYP. 4.0 MAX. 128 Unit s (Minimum instruction execution time = 1 machine cycle) RC oscillation frequency fCC R = 22 k, C = 22 pF VDD = 3.6 to 6.0 V VDD = 2.2 to 3.6 V VDD = 1.8 to 3.6 V VDD = 1.8 to 6.0 V R = 5.1 k, C = 120 pF VDD = 3.6 to 6.0 V VDD = 2.2 to 3.6 V VDD = 1.8 to 3.6 V VDD = 1.8 to 6.0 V Interrupt input high- and low-level width KR4 to KR7 RESET low-level width tRSL tINTH, tINTL INT0 IM02 = 0 IM02 = 1 0.9 0.75 0.5 0.5 0.91 0.76 0.51 0.51 Note 3 10 10 10 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 Note 2 Note 2 Note 2 Note 2 Note 2 Note 2 Note 2 Note 2 1.2 1.15 1.15 1.2 1.1 1.05 1.05 1.1 MHz MHz MHz MHz MHz MHz MHz MHz s s s s Notes 1. The CPU clock () cycle time (minimum instruction execution time) is determined by the time constants of the connected resistor (R) and capacitor (d) and the processor clock control register (PCC). The figure on the right shows the cycle time tCY characteristics against the supply voltage VDD when the system clock is used. 128 tCY vs. VDD (During system clock operation) 2. 3. This is the typical value when VDD = 3.6 V. 2tCY or 128/fCC depending on the setting of the interrupt mode register (IM0). Cycle time tCY ( s) 6 5 Operation guranteed range 4 3 2 1 0.5 0 1 1.8 2 3 4 5 Supply voltage VDD (V) 6 52 PD754144, 754244 * PD754144 EEPROM Characteristics (TA = -40 to +85C, VDD = 1.8 to 6.0 V) Parameter EEPROM write current EEPROM write time EEPROM write times EEWT TA = -40 to +70C TA = -40 to +85C 100000 80000 times/byte times/byte tEEW Symbol IEEW 1.0 MHz, RC oscillation Conditions VDD = 5.0 V 10% VDD = 3.0 V 10% Note MIN. TYP. 4.0 2.0 MAX. 12 6 10.0 Unit mA mA ms 1.0 MHz, RC oscillation 3.8 4.6 Note Set EWTC 4 to 6 so as to be 18 x 28/fCC (4.6 ms: @ fCC = 1.0-MHz operation), considering the variation of the RC oscillation. Comparator Characteristics (TA = -40 to +85C, VDD = 1.8 to 6.0 V) Parameter Comparison accuracy Threshold voltage PTH input voltage AVREF input voltage Comparator circuit current consumption Symbol VACOMP VTH VIPTH VIAVREF IDD5 Conditions MIN. TYP. MAX. 100 Unit mV V V V mA Note 0 1.8 When bit 7 of PTHM is set to 1 1 Note VDD VDD Note The threshold voltage becomes as follows by settings bits 0 to 3 of PTHM. VTH = VIAVREF x (n + 0.5)/16 (n = 0 to 15) 53 PD754144, 754244 * PD754144 AC Timing Test Points VIH (MIN.) VIL (MAX.) VIH (MIN.) VIL (MAX.) VOH (MIN.) VOL (MAX.) VOH (MIN.) VOL (MAX.) Interrupt Input Timing tINTL tINTH INT0, KR4 to KR7 RESET Input Timing tRSL RESET Data Memory STOP Mode Low-Supply Voltage Data Retention Characteristics (TA = -40 to +85C) Parameter Symbol Test Conditions MIN. 0 Release by RESET Release by interrupt request 56/fCC 512/fCC TYP. MAX. Unit Release signal set time tSREL Oscillation stabilization wait time tWAIT s s s 54 PD754144, 754244 * PD754144 Data Retention Timing (on releasing STOP mode by RESET) Internal reset operation HALT mode STOP mode Data retention mode Operation mode VDD tSREL Execution of STOP instruction RESET tWAIT Data Retention Timing (Standby release signal: on releasing STOP mode by interrupt signal) HALT mode STOP mode Data retention mode Operation mode VDD tSREL Execution of STOP instruction Standby release signal (interrupt request) tWAIT 55 PD754144, 754244 13.2 PD754244 Absolute Maximum Ratings (TA = 25C) Parameter Power supply voltage Input voltage Output voltage Output current, high Symbol VDD VI VO IOH Per pin P30, P31, P33, P60 to P63, P80 P32 For all pins Output current, low IOL Note Test Conditions Ratings -0.3 to +7.0 -0.3 to VDD + 0.3 -0.3 to VDD + 0.3 -10 -20 -30 20 90 -40 to +85 Unit V V V mA mA mA mA mA C C Per pin For all pins Operating ambient temperature Storage temperature TA Tstg -65 to +150 Caution If any of the parameters exceeds the absolute maximum ratings, even momentarily, the quality of the product may be impaired. The absolute maximum ratings are values that may physically damage the products. Be sure to use the products within the ratings. Capacitance (TA = 25C, VDD = 0 V) Parameter Input capacitance Output capacitance I/O capacitance Symbol CIN COUT CIO f = 1 MHz Unmeasured pins returned to 0 V Test Conditions MIN. TYP. MAX. 15 15 15 Unit pF pF pF 56 PD754144, 754244 * PD754244 System Clock Oscillator Characteristics (TA = -40 to +85C, VDD = 1.8 to 6.0 V) Resonator Ceramic resonator X1 X2 Recommended Constant Parameter Oscillation frequency (fX) Note1 Testing Conditions MIN. 1.0 TYP. MAX. Unit 6.0Notes2, 3, 4 MHz C1 C2 Oscillation stabilization time Note 5 After VDD reaches MIN. value of oscillation voltage range 1.0 Note1 4 ms Crystal resonator X1 X2 Oscillation frequency(fX) Oscillation stabilization time C1 C2 Note3 6.0 Notes2, 3, 4 MHz VDD = 4.5 to 6.0 V 10 ms 30 ms External clock X1 X2 X1 input frequency (fX) Note1 1.0 6.0 Notes2, 3, 4 MHz X1 input high- and low-level widths (tXH, tXL) 83.3 500 ns Notes 1. 2. Only the oscillator characteristics are shown. For the instruction execution time, refer to AC Characteristics. If the oscillation frequency is 2.1 MHz < fX 4.19 MHz at 1.8 V VDD < 2.0 V, set the processor control register (PCC) to a value other than 0011. If the PCC is set to 0011, the rated machine cycle time of 1.9 s is not satisfied. 3. If the oscillation frequency is 4.19 MHz < fX 6.0 MHz at 1.8 V VDD < 2.0 V, set the processor control register (PCC) to a value other than 0011 or 0010. If the PCC is set to 0011 or 0010, the rated machine cycle time of 1.9 s is not satisfied. 4. If the oscillation frequency is 4.19 MHz < fX 6.0 MHz at 2.0 V VDD < 2.7 V, set the processor control register (PCC) to a value other than 0011. If the PCC is set to 0011, the rated machine cycle time of 0.95 s is not satisfied. 5. Oscillation stabilization time is a time required for oscillation to stabilize after application of VDD, or after the STOP mode has been released. Caution When using the oscillation circuit of the system clock, wire the portion enclosed in dotted lines in the figures as follows to avoid adverse influences on the wiring capacitance: * Keep the wire length as short as possible. * Do not cross other signal lines. * Do not route the wiring in the vicinity of lines though which a high fluctuating current flows. * Always keep the ground point of the capacitor of the oscillation circuit as the same potential as VSS. * Do not connect the power source pattern through which a high current flows. * Do not extract signals from the oscillation circuit. 57 PD754144, 754244 * PD754244 Recommended Oscillator Constants Ceramic resonator (TA = -20 to +80C) Manufacturer Part Number Frequency Recommended Circuit Constant (pF) (MHz) Kyocera KBR-1000F/Y KBR-2.0MS KBR-4.19MSB KBR-4.19MKC PBRC4.19A PBRC4.19B KBR-6.0MSB KBR-6.0MKC PBRC6.00A PBRC6.00B 6.0 1.0 2.0 4.19 C1 100 47 33 -- 33 -- 33 -- 33 -- C2 100 47 33 -- 33 -- 33 -- 33 -- Model with capacitor -- Model with capacitor -- Model with capacitor -- Model with capacitor Oscillation Voltage Range (VDD) MN. (V) 1.8 MAX. (V) 6.0 -- Remark Ceramic resonator (TA = -40 to +80C) Manufacturer Part Number Frequency Recommended Circuit Constant (pF) (MHz) Murata Mfg. Co., Ltd. CSB1000J Note Oscillation Voltage Range (VDD) MIN. (V) 2.0 MAX. (V) 6.0 Remark C1 100 C2 100 1.0 2.0 Rd = 2.2 k -- CSA2.00MG040 CST2.00MG040 CSA4.19MG CST4.19MGW CSA4.19MGU CST4.19MGWU CSA6.00MG CST6.00MGW CSA6.00MGU CST6.00MGWU -- 4.19 30 -- 30 -- 6.0 30 -- 30 -- 1.0 4.19 100 -- -- 30 -- 30 -- 30 -- 30 -- 100 -- 2.0 1.8 2.5 1.8 1.9 Model with capacitor -- Model with capacitor -- Model with capacitor -- Model with capacitor -- Model with capacitor -- Model with capacitor TDK CCR1000K2 CCR4.19MC3 FCR4.19MC5 CCR6.0MC3 FCR6.0MC5 6.0 58 PD754144, 754244 Note When using the CSB1000J (1.0 MHz) made by Murata Mfg. Co., Ltd. as a ceramic resonator, a limiting resistor (Rd = 2.2 k) is necessary (refer to the figure below). This resistor is not necessary when using the other recommended resonators. X1 CSB1000J X2 Rd * C1 * C2 * Caution The oscillator constants and oscillation voltage range indicate conditions for stable oscillation, but do not guarantee oscillation frequency accuracy. If oscillation frequency accuracy is required for actual circuits, it is necessary to adjust the oscillation frequency of the oscillator in the actual circuit. Please contact directly the manufacturer of the resonator to be used. 59 PD754144, 754244 * PD754244 DC Characteristics (TA = -40 to +85C, VDD = 1.8 to 6.0 V) Parameter High-level output current Symbol IOH Per pin Conditions P30, P31, P33, P60 to P63, P80 P32, VDD = 3.0 V, VOH = VDD - 2.0 V Total of all pins Low-level output current High-level input voltage VIH2 Ports 6 to 8, KRREN, RESET VIH3 Low-level input voltage VIL2 Ports 6 to 8, KRREN, RESET VIH3 High-level output voltage Low-level output voltage VOL VOH X1 VDD = 4.5 to 6.0 V, IOH = -1.0 mA VDD = 1.8 to 6.0 V, IOH = -100 A VDD = 4.5 to 6.0 V Port 3, IOL = 15 mA Ports 6, 8, IOL = 1.6 mA VDD = 1.8 to 6.0 V, IOH = 400 A High-level input leakage current Low-level input leakage current High-level output leakage current Low-level output leakage current On-chip pull-up resistance RL1 RL2 VIN = 0 V Port 3, 6, 8 Port 7, RESET (mask option) 50 50 100 100 200 200 k k ILOL VOUT = 0 V -3.0 A ILIH1 ILIH2 ILIL1 ILIH2 ILOH VOUT = VDD VIN = 0 V VIN = VDD Pins other than X1 X1 Pins other than X1 X1 0.5 3.0 20 -3.0 -20 3.0 V A A A A A VIL1 X1 Port 3 2.7 V VDD 6.0 V 1.8 V VDD < 2.7 V 2.7 V VDD 6.0 V 1.8 V VDD < 2.7 V VIH1 IOL Per pin Total of all pins Port 3 2.7 V VDD 6.0 V 1.8 V VDD < 2.7 V 2.7 V VDD 6.0 V 1.8 V VDD < 2.7 V 0.7VDD 0.9VDD 0.8VDD 0.9VDD VDD - 0.1 0 0 0 0 0 VDD - 1.0 VDD - 0.5 0.6 2.0 0.4 -20 15 45 VDD VDD VDD VDD VDD 0.3VDD 0.1VDD 0.2VDD 0.1VDD 0.1 mA mA mA V V V V V V V V V V V V V V -7 -15 mA MIN. TYP. MAX. -5 Unit mA 60 PD754144, 754244 * PD754244 DC Characteristics (TA = -40 to +85C, VDD = 1.8 to 6.0 V) Parameter Power supply current Note 1 Symbol IDD1 4.19-MHz crystal IDD2 oscillation Conditions VDD = 5.0 V 10% VDD = 3.0 V 10% HALT Note 2 Note 3 MIN. TYP. 1.5 0.23 0.64 0.20 MAX. 5.0 1.0 3.0 0.9 5 Unit mA mA mA mA VDD = 5.0 V 10% VDD = 3.0 V 10% C1 = C2 = 22 pF mode IDD3 X1 = 0 V STOP mode VDD = 1.8 to 6.0 V TA = 25C VDD = 3.0 V 10% TA = -40 to +40C 0.1 0.1 A A A A 1 3 1 Notes 1. 2. 3. The current flowing through the on-chip pull-up resistor, the current during EEPROM writing time, and the current during the program threshold port (PTH) operation are not included. When the device is operated in the high-speed mode by setting the processor clock control register (PCC) to 0011H When the device is operated in the low-speed mode by setting PCC to 0000H 61 PD754144, 754244 * PD754244 AC Characteristics (TA = -40 to +85C, VDD = 1.8 to 6.0 V) Parameter CPU clock cycle time Note 1 Symbol tCY Test Conditions VDD = 1.8 to 2.0 V VDD = 2.0 to 2.7 V VDD = 2.7 to 6.0 V MIN. 1.9 0.95 0.67 TYP. MAX. 64.0 64.0 64.0 Unit s s s s s s s (Minimum instruction execution time = 1 machine cycle) Interrupt input high- and low-level width tINTH, tINTL INT0 IM02 = 0 IM02 = 1 Note 2 10 10 10 KR4 to KR7 RESET low-level width tRSL Notes 1. The CPU clock () cycle time (minimum instruction execution time) is determined by the oscillation frequency of the connected resonator (or external clock) and the processor clock control register (PCC). The figure on the right shows the cycle time tCY characteristics against the supply voltage VDD when the system clock is used. 64 60 6 5 Operation guranteed range Cycle time tCY ( s) 4 3 tCY vs. VDD (During system clock operation) 2. 2tCY or 128/fX depending on the setting of the interrupt mode register (IM0). 2 1.9 1 0.95 0.67 0.5 0 1 1.8 2 2.7 3 4 5 Supply voltage VDD (V) 6 62 PD754144, 754244 * PD754244 EEPROM Characteristics (TA = -40 to +85C, VDD = 1.8 to 6.0 V) Parameter EEPROM write current EEPROM write time EEPROM write times EEWT TA = -40 to +70C TA = -40 to +85C 100000 80000 times/byte times/byte tEEW Symbol IEEW 4.19 MHz, crystal oscillation Conditions VDD = 5.0 V 10% VDD = 3.0 V 10% MIN. TYP. 4.5 2.0 MAX. 15 6 10.0 Unit mA mA ms 3.8 Comparator Characteristics (TA = -40 to +85C, VDD = 1.8 to 6.0 V) Parameter Comparison accuracy Threshold voltage PTH input voltage AVREF input voltage Comparator circuit current consumption Symbol VACOMP VTH VIPTH VIAVREF IDD5 Conditions MIN. TYP. MAX. 100 Unit mV V V V mA Note 0 1.8 When bit 7 of PTHM is set to 1 1 Note VDD VDD Note The threshold voltage becomes as follows by settings bits 0 to 3 of PTHM. VTH = VIAVREF x (n + 0.5)/16 (n = 0 to 15) 63 PD754144, 754244 * PD754244 AC Timing Test Points (Excluding X1 Input) VIH (MIN.) VIL (MAX.) VIH (MIN.) VIL (MAX.) VOH (MIN.) VOL (MAX.) VOH (MIN.) VOL (MAX.) Clock Timing 1/fX tXL tXH X1 input VDD - 0.1 V 0.1 V 64 PD754144, 754244 * PD754244 Interrupt Input Timing tINTL tINTH INT0, KR4 to KR7 RESET Input Timing tRSL RESET Data Memory STOP Mode Low-Supply Voltage Data Retention Characteristics (TA = -40 to +85 C) Parameter Symbol Test Conditions MIN. 0 Release by RESET Release by interrupt request Note 2 Note 3 TYP. MAX. Unit Release signal set time tSREL Oscillation stabilization wait time Note 1 s ms ms tWAIT Notes 1. 2. 3. BTM3 The oscillation stabilization wait time is the time during which the CPU operation is stopped to avoid unstable operation at oscillation start. 217 /fx and 215/fx can be selected with mask option. Depends on setting of basic interval timer mode register (BTM) (see table below). BTM2 BTM1 BTM0 When fX = 4.19 MHz Wait Time When fX = 6.0 MHz 220/fX 217/fX 215/fX 213/fX (Approx. 175 ms) (Approx. 21.8 ms) (Approx. 5.46 ms) (Approx. 1.37 ms) - - - - 0 0 1 1 0 1 0 1 0 1 1 1 220/fX 217/fX 215/fX 213/fX (Approx. 250 ms) (Approx. 31.3 ms) (Approx. 7.81 ms) (Approx. 1.95 ms) 65 PD754144, 754244 Data Retention Timing (on releasing STOP mode by RESET) Internal reset operation HALT mode STOP mode Data retention mode Operation mode VDD tSREL Execution of STOP instruction RESET tWAIT Data Retention Timing (Standby release signal: on releasing STOP mode by interrupt signal) HALT mode STOP mode Data retention mode Operation mode VDD tSREL Execution of STOP instruction Standby release signal (interrupt request) tWAIT 66 PD754144, 754244 14. CHARACTERISTICS CURVES (REFERENCE VALUES) 14.1 PD754144 IDD vs. VDD (RC Oscillation, R = 22 k, C = 22 pF) (TA = 25C) 10 5.0 1.0 PCC = 0011 PCC = 0010 PCC = 0001 PCC = 0000 System clock HALT mode 0.5 Power Supply Current IDD (mA) 0.1 0.05 0.01 0.005 CL1 CL2 22 k 22 pF 0.001 0 1 2 3 4 5 6 7 8 Power Supply Voltage VDD (V) 67 PD754144, 754244 * PD754144 IDD vs. VDD (RC Oscillation, R = 5.1 k, C = 120 pF) (TA = 25C) 10 5.0 1.0 PCC = 0011 PCC = 0010 PCC = 0001 PCC = 0000 and System clock HALT mode 0.5 Power Supply Current IDD (mA) 0.1 0.05 0.01 0.005 CL1 CL2 5.1 k 120 pF 0.001 0 1 2 3 4 5 6 7 8 Power Supply Voltage VDD (V) 68 PD754144, 754244 14.2 PD754244 IDD vs. VDD (System Clock: 6.0-MHz Crystal Resonator) (TA = 25C) 10 5.0 PCC = 0011 PCC = 0010 1.0 PCC = 0001 PCC = 0000 System clock HALT mode 0.5 Power Supply Current IDD (mA) 0.1 0.05 0.01 0.005 X1 X2 Crystal resonator 6.0 MHz 22 pF 22 pF 0.001 0 1 2 3 4 5 6 7 8 Power Supply Voltage VDD (V) 69 PD754144, 754244 * PD754244 IDD vs. VDD (System Clock: 4.19-MHz Crystal Resonator) (TA = 25C) 10 5.0 PCC = 0011 1.0 PCC = 0010 PCC = 0001 PCC = 0000 System clock HALT mode 0.5 Power Supply Current IDD (mA) 0.1 0.05 0.01 0.005 X1 X2 Crystal resonator 4.19 MHz 22 pF 22 pF 0.001 0 1 2 3 4 5 6 7 8 Power Supply Voltage VDD (V) 70 PD754144, 754244 * PD754244 IDD vs. VDD (System Clock: 2.0-MHz Crystal Resonator) (TA = 25C) 10 5.0 1.0 PCC = 0011 PCC = 0010 PCC = 0001 PCC = 0000 0.5 Power Supply Current IDD (mA) System clock HALT mode 0.1 0.05 0.01 0.005 X1 X2 Crystal resonator 2.0 MHz 47 pF 47 pF 0.001 0 1 2 3 4 5 6 7 8 Power Supply Voltage VDD (V) 71 PD754144, 754244 15. RC OSCILLATION FREQUENCY CHARACTERISTICS EXAMPLES (REFERENCE VALUES) fCC vs. VDD (RC Oscillation, R = 22 k, C = 22 pF) (TA = -40C) 2.0 CL1 CL2 22 k 22 pF System Clock Frequency fCC (MHz) 1.0 Sample C Sample B 0.5 Sample A 0 1 2 3 4 5 6 7 8 Power Supply Voltage VDD (V) (TA = 25C) 2.0 CL1 CL2 22 k 22 pF System Clock Frequency fCC (MHz) 1.0 Sample C Sample B Sample A 0.5 0 1 2 3 4 5 6 7 8 Power Supply Voltage VDD (V) (TA = 85C) 2.0 CL1 CL2 22 k 22 pF System Clock Frequency fCC (MHz) 1.0 Sample C Sample B Sample A 0.5 0 1 2 3 4 5 6 7 8 Power Supply Voltage VDD (V) 72 PD754144, 754244 fCC vs. TA (RC Oscillation, R = 22 k, C = 22 pF) (Sample A) 2.0 CL1 CL2 22 k 22 pF System Clock Frequency fCC (MHz) 1.0 VDD = 5.0 V VDD = 6.0 V VDD = 3.0 V VDD = 2.2 V VDD = 1.8 V 0.5 -60 -40 -20 0 +20 +40 +60 +80 +100 Operating Ambient Temperature TA (C) (Sample B) 2.0 System Clock Frequency fCC (MHz) CL1 CL2 22 k 22 pF VDD = 5.0 V VDD = 6.0 V VDD = 3.0 V VDD = 2.2 V VDD = 1.8 V 1.0 0.5 -60 -40 -20 0 +20 +40 +60 +80 +100 C) Operating Ambient Temperature TA ( (Sample C) 2.0 System Clock Frequency fCC (MHz) CL1 CL2 22 k 22 pF VDD = 5.0 V VDD = 6.0 V VDD = 3.0 V VDD = 2.2 V VDD = 1.8 V 1.0 0.5 -60 -40 -20 0 +20 +40 +60 +80 +100 Operating Ambient Temperature TA (C) 73 PD754144, 754244 fCC vs. VDD (RC Oscillation, R = 5.1 k , C = 120 pF) (TA = -40C) 2.0 CL1 CL2 5.1 k 120 pF System Clock Frequency fCC (MHz) 1.0 Sample C Sample B 0.5 Sample A 0 1 2 3 4 5 6 7 8 Power Supply Voltage VDD (V) (TA = 25C) 2.0 CL1 CL2 5.1 k 120 pF System Clock Frequency fCC (MHz) 1.0 Sample C Sample B Sample A 0.5 0 1 2 3 4 5 6 7 8 Power Supply Voltage VDD (V) (TA = 85C) 2.0 System Clock Frequency fCC (MHz) CL1 CL2 5.1 k 120 pF 1.0 Sample C Sample B Sample A 0.5 0 1 2 3 4 5 6 7 8 Power Supply Voltage VDD (V) 74 PD754144, 754244 fCC vs. TA (RC Oscillation, R = 5.1 k, C = 120 pF) (Sample A) 2.0 CL1 CL2 5.1 k 120 pF System Clock Frequency fCC (MHz) 1.0 VDD = 5.0 V VDD = 6.0 V VDD = 3.0 V VDD = 2.2 V VDD = 1.8 V 0.5 -60 -40 -20 0 +20 +40 +60 +80 +100 Operating Ambient Temperature TA (C) (Sample B) 2.0 System Clock Frequency fCC (MHz) CL1 CL2 5.1 k 120 pF VDD = 5.0 V and VDD = 6.0 V VDD = 3.0 V VDD = 2.2 V VDD = 1.8 V 1.0 0.5 -60 -40 -20 0 +20 +40 +60 +80 +100 Operating Ambient Temperature TA (C) (Sample C) 2.0 System Clock Frequency fCC (MHz) CL1 CL2 5.1 k 120 pF 1.0 VDD = 5.0 V VDD = 6.0 V VDD = 3.0 V VDD = 2.2 V VDD = 1.8 V 0.5 -60 -40 -20 0 +20 +40 +60 +80 +100 Operating Ambient Temperature TA (C) 75 PD754144, 754244 16. PACKAGE DRAWINGS 20-pin Plastic SOP (300 mils) 20 11 detail of lead end P 1 A 10 H G I J L C D E F NOTE Each lead centerline is located within 0.12 mm (0.005 inch) of its true position (T.P.) at maximum material condition. ITEM A B C D E F G H I J K L M N P MILLIMETERS 12.70.3 0.78 MAX. 1.27 (T.P.) 0.42 +0.08 -0.07 0.10.1 1.8 MAX. 1.550.05 7.70.3 5.60.2 1.1 0.22 +0.08 -0.07 0.60.2 0.12 0.10 3 +7 -3 INCHES 0.5000.012 0.031 MAX. 0.050 (T.P.) 0.017 +0.003 -0.004 0.0040.004 0.071 MAX. 0.0610.002 0.3030.012 0.220 +0.009 -0.008 0.043 0.009 +0.003 -0.004 0.024 +0.008 -0.009 0.005 0.004 3 +7 -3 P20GM-50-300B, C-5 B N K M M 76 PD754144, 754244 20-pin Plastic shrink SOP (300 mils) 20 11 detail of lead end P 1 A 10 H F G S I J E C D NOTE L N S K B ITEM A B C D E F G H I J K L M N P MILLIMETERS 6.70.3 0.575 MAX. 0.65 (T.P.) 0.32 +0.08 -0.07 0.125 0.075 2.0 MAX. 1.70.1 8.1 0.3 6.1 0.2 1.0 0.2 0.15 +0.10 -0.05 0.5 0.2 0.12 0.10 3 +7 -3 INCHES 0.264 +0.012 -0.013 0.023 MAX. 0.026 (T.P.) 0.013 +0.003 -0.004 0.005 0.003 0.079 MAX. 0.067 +0.004 -0.005 0.319 0.012 0.240 0.008 0.039 +0.009 -0.008 0.006 +0.004 -0.002 0.020 +0.008 -0.009 0.005 0.004 3 +7 -3 P20GM-65-300B-3 M M 1. Controlling dimension millimeter. 2. Each lead centerline is located within 0.12 mm (0.005 inch) of its true position (T.P.) at maximum material condition. 77 PD754144, 754244 17. RECOMMENDED SOLDERING CONDITIONS Solder the PD754244 under the following recommended conditions. For the details on the recommended soldering conditions, refer to Information Document "Semiconductor Device Mounting Technology Manual (C10535E)". For the soldering method and conditions other than those recommended, consult an NEC representative. Table 17-1. Soldering Conditions of Surface Mount Type (1/2) (1) PD754244GS-xxx-GJG: 20-pin plastic shrink SOP (300 mil, 0.65-mm pitch) Soldering Method Infrared ray reflow Soldering Conditions Package peak temperature: 235C, Reflow time: 30 seconds max. (210C min.), Number of reflow process: 2 max. VPS Package peak temperature: 215C, Reflow time: 40 seconds max. (200C min.), Number of reflow process: 2 max. Wave soldering Solder bath temperature: 260C max., Flow time: 10 seconds max., Number of flow process: 1 Preheating temperature: 120C max. (package surface temperature) Partial heating Pin temperature: 300C max., Time: 3 seconds max. (per side of device) - WS60-00-1 VP15-00-2 Symbol IR35-00-2 Caution Do not use different soldering methods together (except for partial heating). (2) PD754144GS-xxx-GJG: 20-pin plastic shrink SOP (300 mil, 0.65-mm pitch) Soldering Method Infrared ray reflow Soldering Conditions Package peak temperature: 235C, Reflow time: 30 seconds max. (210C min.), Number of reflow process: 3 max. VPS Package peak temperature: 215C, Reflow time: 40 seconds max. (200C min.), Number of reflow process: 3 max. Wave soldering Solder bath temperature: 260C max., Flow time: 10 seconds max., Number of flow process: 1 Preheating temperature: 120C max. (package surface temperature) Partial heating Pin temperature: 300C max., Time: 3 seconds max. (per side of device) - WS60-00-1 VP15-00-3 Symbol IR35-00-3 Caution Do not use different soldering methods together (except for partial heating). 78 PD754144, 754244 Table 17-1. Soldering Conditions of Surface Mount Type (2/2) (3) PD754144GS-xxx-BA5: 20-pin plastic SOP (300 mil, 1.27-mm pitch) PD754244GS-xxx-BA5: 20-pin plastic SOP (300 mil, 1.27-mm pitch) Soldering Method Infrared ray reflow Soldering Conditions Package peak temperature: 235C, Reflow time: 30 seconds max. (210C min.), Number of reflow process: 2 max. Exposure limit: 7 daysNote (afterward, 10-hour pre-baking at 125C is required) VPS Package peak temperature: 215C, Reflow time: 40 seconds max. (200C min.), Number of reflow process: 2 max. Exposure limit: 7 daysNote (afterward, 10-hour pre-baking at 125C is required) Wave soldering Solder bath temperature: 260C max., Flow time: 10 seconds max., Number of flow process: 1 Preheating temperature: 120C max. (package surface temperature) Exposure limit: 7 daysNote (afterward, 10-hour pre-baking at 125C is required) Partial heating Pin temperature: 300C max., Time: 3 seconds max. (per side of device) - WS60-107-1 VP15-107-2 Symbol IR35-107-2 Note Maximum number of days during which the product can be stored at a temperature of 25C and a relative humidity of 65% or less after dry-pack package is opened. Caution Do not use different soldering methods together (except for partial heating). 79 PD754144, 754244 APPENDIX A. COMPARISON OF FUNCTIONS AMONG PD754144, 754244, AND 75F4264 Item Program memory PD754144 Mask ROM 0000H to 0FFFH (4096 x 8 bits) PD754244 PD75F4264 Flash memory 0000H to 0FFFH (4096 x 8 bits) Note Data memory Static RAM 000H to 07FH (128 x 4 bits) EEPROM 400H to 41FH (16 x 8 bits) 400H to 43FH (32 x 8 bits) CPU General-purpose register Instruction execution time 75XL CPU (4 bits x 8 or 8 bits x 4) x 4 banks * 4, 8, 16, 64 s (@ fCC = 1.0-MHz operation) * 0.67, 1.33, 2.67, 10.7 s (@ fX = 6.0-MHz operation) * 0.95, 1.91, 3.81, 15.3 s (@ fX = 4.19-MHz operation) I/O port CMOS input CMOS I/O Total 4 (on-chip pull-up resistor can be connected by mask option) 9 (on-chip pull-up resistor connection can be specified by means of software) 13 RC oscillator (resistor and capacitor are connected externally) Ceramic/crystal oscillator System clock oscillator Start-up time after reset 56/fCC 217 /fX, 215/fX (can be selected by mask option) 215 /fX Standby mode release time 2 /fCC 9 220 /fX, 217/fX, 2 15/fX, 213 /fX (can be selected by the setting of BTM) Timer 4 channels * 8-bit timer counter: 3 channels (can be used as 16-bit timer counter) * Basic interval timer/watchdog timer: 1 channel A/D converter None * 8-bit resolution x 2 channels (successive approximation, hardware control) * Can be operated from VDD = 1.8 V Programmable threshold port Vectored interrupt Test input Power supply voltage Operating ambient temperature Package 2 channels External: 1, internal: 5 External: 1 (key return reset function available) VDD = 1.8 to 6.0 V TA = -40 to +85C * 20-pin plastic SOP (300 mil, 1.27-mm pitch) * 20-pin plastic shrink SOP (300 mil, 0.65-mm pitch) * 20-pin plastic SOP (300 mil, 1.27-mm pitch) Note Under development 80 PD754144, 754244 APPENDIX B DEVELOPMENT TOOLS The following development tools are provided for system development using the PD754244. In the 75XL series, the relocatable assembler which is common to the series is used in combination with the device file of each product. Language processor RA75X relocatable assembler Part number (product name) Host machine OS PC-9800 series MS-DOSTM Ver. 3.30 to Ver. 6.2Note IBM PC/ATTM and compatible machines Refer to "OS for IBM PC" 3.5-inch 2HC 5-inch 2HC Distribution media 3.5-inch 2HD 5-inch 2HD S5A13RA75X S5A10RA75X S7B13RA75X S7B10RA75X Device file Host machine OS PC-9800 series MS-DOS Ver. 3.30 to Ver. 6,2Note IBM PC/AT and compatible machines Refer to "OS for IBM PC" 3.5-inch 2HC 5-inch 2HC Distribution media 3.5-inch 2HD 5-inch 2HD Part number (product name) S5A13DF754244 S5A10DF754244 S7B13DF754244 S7B10DF754244 Note Ver.5.00 or later have the task swap function, but it cannot be used for this software. Remark Operation of the assembler and device file are guaranteed only on the above host machine and OSs. 81 PD754144, 754244 Debugging tool The in-circuit emulators (IE-75000-R and IE-75001-R) are available as the program debugging tool for the PD754244. The system configurations are described as follows. Hardware IE-75000-R Note 1 In-circuit emulator for debugging the hardware and software when developing application systems that use the 75X series and 75XL series. When developing the PD754244, the emulation board IE-75300-R-EM and emulation probe EP-754144GS-R that are sold separately must be used with the IE-75000-R. By connecting with the host machine, efficient debugging can be made. It contains the emulation board IE-75000-R-EM which is connected. In-circuit emulator for debugging the hardware and software when developing application systems that use the 75X series and 75XL series. When developing the PD754244, the emulation board IE-75300-R-EM and emulation probe EP-754144GS-R which are sold separately must be used with the IE-75001-R. By connecting the host machine, efficient debugging can be made. Emulation board for evaluating the application systems that use the PD754244. It must be used with the IE-75000-R or IE-75001-R. Emulation probe for the PD754244GS. It must be connected to IE-75000-R (or IE-75001-R) and IE-75300-R-EM. It is supplied with the flexible boards EV-9500GS-20 (supporting 20-pin plastic shrink SOPs) and EV-9501GS-20 (supporting 20-pin plastic SOPs) which facillitate connection to a target system. Connects the IE-75000-R or IE-75001-R to a host machine via RS-232-C and Centronix I/F and controls the above hardware on a host machine. Host machine OS PC-9800 series MS-DOS Ver. 3.30 to Ver. 6.2 Note 2 IBM PC/AT and its compatible machine Refer to "OS for IBM PC" 3.5-inch 2HC 5-inch 2HC Distribution media 3.5-inch 2HD 5-inch 2HD Part No. (product name) IE-75001-R IE-75300-R-EM EP-754144GS-R EV-9500GS-20 EV-950IGS-20 Software IE control program S5A13IE75X S5A10IE75X S7B13IE75X S7B10IE75X Notes 1. 2. Maintenance parts Ver.5.00 or later have the task swap function, but it cannot be used for this software. Remark Operation of the IE control program is guaranteed only on the above host machines and OSs. 82 PD754144, 754244 OS for IBM PC The following IBM PC OS's are supported. OS PC DOS TM Version Ver. 5.02 to Ver. 6.3 J6.1/VNote to J6.3/VNote Ver. 5.0 to Ver. 6.22 5.0/V Note to J6.2/V Note J5.02/VNote MS-DOS IBM DOSTM Note Supported only English mode. Caution Ver. 5.0 and later have the task swap function, but it cannot be used for operating systems above. 83 PD754144, 754244 APPENDIX C. RELATED DOCUMENTS The related documents indicated in this publication may include preliminary versions. However, preliminary versions are not marked as such. Device related documents Document Number Document Name Japanese English This document U10676E U10453E PD754144, 754244 Data Sheet PD754144, 754244 User's Manual 75XL Series Selection Guide U10040J U10676J U10453J Development tool related documents Document Number Document Name Japanese Hardware IE-75000-R/IE-75001-R User's Manual IE-75300-R-EM User's Manual EP-754144GS-R User's Manual Software RA75X Assembler Package User's Manual Operation Language EEU-846 U11354J U10695J EEU-731 EEU-730 English EEU-1416 U11354E U10695E EEU-1346 EEU-1363 Other related documents Document Number Document Name Japanese IC Package Manual Semiconductor Device Mounting Technology Manual Quality Grades on NEC Semiconductor Devices NEC Semiconductor Device Reliability/Quality Control System Static Electricity Discharge (ESD) Test Guide to Quality Assurance for Semiconductor Devices Microcomputer Related Product Guide - Other Manufacturers C10943X C10535J C11531J C10983J MEM-539 C11893J U11416J C10535E C11531E C10983E - MEI-1202 - English Caution These documents are subject to change without notice. Be sure to read the latest documents. 84 PD754144, 754244 [MEMO] 85 PD754144, 754244 NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be Semiconductor adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. bare hands. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS device behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. 86 PD754144, 754244 Regional Information Some information contained in this document may vary from country to country. Before using any NEC product in your application, please contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify: * Device availability * Ordering information * Product release schedule * Availability of related technical literature * Development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, AC supply voltages, and so forth) * Network requirements In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. NEC Electronics Inc. (U.S.) Santa Clara, California Tel: 408-588-6000 800-366-9782 Fax: 408-588-6130 800-729-9288 NEC Electronics (Germany) GmbH Benelux Office Eindhoven, The Netherlands Tel: 040-2445845 Fax: 040-2444580 NEC Electronics Hong Kong Ltd. Hong Kong Tel: 2886-9318 Fax: 2886-9022/9044 NEC Electronics Hong Kong Ltd. NEC Electronics (France) S.A. Velizy-Villacoublay, France Tel: 01-30-67 58 00 Fax: 01-30-67 58 99 Seoul Branch Seoul, Korea Tel: 02-528-0303 Fax: 02-528-4411 NEC Electronics (Germany) GmbH Duesseldorf, Germany Tel: 0211-65 03 02 Fax: 0211-65 03 490 NEC Electronics (France) S.A. NEC Electronics (UK) Ltd. Milton Keynes, UK Tel: 01908-691-133 Fax: 01908-670-290 Spain Office Madrid, Spain Tel: 01-504-2787 Fax: 01-504-2860 NEC Electronics Singapore Pte. Ltd. United Square, Singapore 1130 Tel: 65-253-8311 Fax: 65-250-3583 NEC Electronics Taiwan Ltd. NEC Electronics Italiana s.r.1. Milano, Italy Tel: 02-66 75 41 Fax: 02-66 75 42 99 NEC Electronics (Germany) GmbH Scandinavia Office Taeby, Sweden Tel: 08-63 80 820 Fax: 08-63 80 388 Taipei, Taiwan Tel: 02-719-2377 Fax: 02-719-5951 NEC do Brasil S.A. Cumbica-Guarulhos-SP, Brasil Tel: 011-6465-6810 Fax: 011-6465-6829 J98. 2 87 PD754144, 754244 [MEMO] The PD754244 is manufactured and sold based on a licence contract with CP8 Transac regarding the EEPROM microcomputer patent. This product cannot be used for an IC card (SMART CARD). The export of this product from Japan is regulated by the Japanese government. To export this product may be prohibited without governmental license, the need for which must be judged by the customer. The export or re-export of this product from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales representative. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. NEC devices are classified into the following three quality grades: "Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance. Anti-radioactive design is not implemented in this product. M4 96.5 EEPROM is a trademark of NEC Corporation. MS-DOS is either a registered trademark or a trademark of Microsoft Corporation in the United States and/or other countries. IBM DOS, PC/AT, and PC DOS are trademarks of International Business Machines Corporation. 86 |
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